| /src/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| grph_object_ctrl_defs.h | 239 uint8_t lane0:2; /* Mapping for lane 0 */ member in struct:ddi_channel_mapping::mapping
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
|
| armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-j721e-main.dtsi | 49 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
50 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
51 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
52 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
54 /* SERDES4 lane0/1/2/3 select */
|
| k3-j7200-main.dtsi | 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
|
| k3-am64-main.dtsi | 50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| msm8996.dtsi | 611 reset-names = "lane0";
|
