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    Searched refs:lane_settings (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
link_service_types.h 75 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; member in struct:link_training_settings
bios_parser_types.h 156 uint32_t lane_settings; member in struct:bp_transmitter_control
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_dp.c 282 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
284 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
287 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
290 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
347 link->cur_lane_setting = lt_settings->lane_settings[0];
390 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
392 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
395 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_debugfs.c 412 link_lane_settings.lane_settings[r].VOLTAGE_SWING =
414 link_lane_settings.lane_settings[r].PRE_EMPHASIS =
416 link_lane_settings.lane_settings[r].POST_CURSOR2 =
660 link_training_settings.lane_settings[i] = link->cur_lane_setting;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_link_encoder.c 1139 link_settings->lane_settings[lane].VOLTAGE_SWING;
1141 link_settings->lane_settings[lane].PRE_EMPHASIS;
1149 link_settings->lane_settings[lane].POST_CURSOR2;
1153 cntl.lane_settings = training_lane_set.raw;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_link_encoder.c 1105 link_settings->lane_settings[lane].VOLTAGE_SWING;
1107 link_settings->lane_settings[lane].PRE_EMPHASIS;
1115 link_settings->lane_settings[lane].POST_CURSOR2;
1119 cntl.lane_settings = training_lane_set.raw;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table.c 444 params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
572 params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
705 params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings);
802 params.ucDPLaneSet = (uint8_t) cntl->lane_settings;
852 params.ucDPLaneSet = (uint8_t)cntl->lane_settings;
amdgpu_command_table2.c 270 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_dp_types.h 118 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; member in struct:dc_link_training_settings

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