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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv730_dpm.c 251 &table->ACPIState.levels[0].vddc);
252 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
254 table->ACPIState.levels[0].gen2XSP =
258 &table->ACPIState.levels[0].vddc);
259 table->ACPIState.levels[0].gen2PCIE = 0;
301 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
302 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
303 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
304 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
305 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl)
    [all...]
radeon_rv740_dpm.c 339 &table->ACPIState.levels[0].vddc);
340 table->ACPIState.levels[0].gen2PCIE =
343 table->ACPIState.levels[0].gen2XSP =
347 &table->ACPIState.levels[0].vddc);
348 table->ACPIState.levels[0].gen2PCIE = 0;
378 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
379 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
380 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
381 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
382 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl)
    [all...]
radeon_cypress_dpm.c 781 &smc_state->levels[0],
788 &smc_state->levels[1],
795 &smc_state->levels[2],
800 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
801 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
802 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
805 smc_state->levels[0].ACIndex = 2;
806 smc_state->levels[1].ACIndex = 3;
807 smc_state->levels[2].ACIndex = 4;
809 smc_state->levels[0].ACIndex = 0
    [all...]
radeon_rv770_dpm.c 294 smc_state->levels[i].aT = cpu_to_be32(a_t);
300 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
314 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
316 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
690 &smc_state->levels[0],
697 &smc_state->levels[1],
704 &smc_state->levels[2],
709 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
710 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
711 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3
    [all...]
radeon_sumo_dpm.c 352 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
416 m_a = asi * ps->levels[i].sclk / 100;
675 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
767 sumo_program_power_level(rdev, &new_ps->levels[i], i);
849 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
850 current_ps->levels[current_ps->num_levels - 1].sclk)
867 if (new_ps->levels[new_ps->num_levels - 1].sclk <
868 current_ps->levels[current_ps->num_levels - 1].sclk)
1058 current_vddc = current_ps->levels[current_index].vddc_index;
1059 current_sclk = current_ps->levels[current_index].sclk
    [all...]
radeon_ni_dpm.c 1696 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
1698 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
1700 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
1702 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
1704 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
1706 table->initialState.levels[0].mclk.vDLL_CNTL =
1708 table->initialState.levels[0].mclk.vMPLL_SS =
1710 table->initialState.levels[0].mclk.vMPLL_SS2 =
1712 table->initialState.levels[0].mclk.mclk_value =
1715 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL
    [all...]
radeon_trinity_dpm.c 854 trinity_program_power_level(rdev, &new_ps->levels[i], i);
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
975 current_ps->levels[current_ps->num_levels - 1].sclk)
988 if (new_ps->levels[new_ps->num_levels - 1].sclk <
989 current_ps->levels[current_ps->num_levels - 1].sclk)
1336 ps->levels[0] = pi->boot_pl;
1359 pi->current_ps.levels[0] = pi->boot_pl;
1414 current_vddc = current_ps->levels[current_index].vddc_index;
1415 current_sclk = current_ps->levels[current_index].sclk;
1421 ps->levels[0].vddc_index = current_vddc
    [all...]
  /src/sys/arch/macppc/macppc/
pic_heathrow.c 157 uint32_t levels; local
163 levels = in32rb(INT_STATE_REG_H);
164 if (levels & mask) {
171 levels = in32rb(INT_STATE_REG_L);
172 if (levels & mask) {
198 uint32_t irqs, events, levels; local
204 levels = in32rb(INT_LEVEL_REG_L) & heathrow->enable_mask_l;
205 events |= levels & heathrow->level_mask_l;
212 levels = in32rb(INT_LEVEL_REG_L) & heathrow->enable_mask_h;
213 events |= levels & heathrow->level_mask_h
    [all...]
pic_ohare.c 178 uint32_t levels; local
183 levels = in32rb(INT_STATE_REG);
184 if (levels & mask) {
204 uint32_t irqs, events, levels; local
209 levels = in32rb(INT_LEVEL_REG) & ohare->enable_mask;
210 events |= levels & ohare->level_mask;
270 printf("levels: %08x\n", in32rb(INT_LEVEL_REG));
  /src/tests/modules/x86_pte_tester/
x86_pte_tester.c 51 vaddr_t levels[NLEVEL]; member in struct:__anon7921
89 pd_entry_t *pd = (pd_entry_t *)tester_ctx.levels[0];
92 pmap_kenter_pa(tester_ctx.levels[0], pa, VM_PROT_READ, 0);
102 pmap_kremove(tester_ctx.levels[0], PAGE_SIZE);
109 pd_entry_t *pd = (pd_entry_t *)tester_ctx.levels[1];
113 pmap_kenter_pa(tester_ctx.levels[1], pa, VM_PROT_READ, 0);
129 pmap_kremove(tester_ctx.levels[1], PAGE_SIZE);
136 pd_entry_t *pd = (pd_entry_t *)tester_ctx.levels[2];
140 pmap_kenter_pa(tester_ctx.levels[2], pa, VM_PROT_READ, 0);
156 pmap_kremove(tester_ctx.levels[2], PAGE_SIZE)
    [all...]
  /src/sys/dev/fdt/
pwm_fan.c 80 const u_int *levels; local
91 levels = fdtbus_get_prop(phandle, "cooling-levels", &len);
93 aprint_error(": couldn't get 'cooling-levels' property\n");
99 sc->sc_levels[n] = be32toh(levels[n]);
103 aprint_normal(" (levels");
pwm_backlight.c 88 const u_int *levels; local
109 levels = fdtbus_get_prop(phandle, "brightness-levels", &len);
110 if (levels != NULL) {
114 sc->sc_levels[n] = be32toh(levels[n]);
242 0, CTLTYPE_STRING, "levels", NULL,
  /src/sys/arch/x86/x86/
x86_softintr.c 169 /* First, figure out which levels each IRQ uses. */
172 int levels = 0; local
179 levels |= 1 << q->ih_level;
180 intrlevel[irq] = levels;
181 if (levels)
  /src/lib/libc/db/btree/
bt_debug.c 307 int levels; local
335 /* Count the levels of the tree. */
336 for (i = P_ROOT, levels = 0 ;; ++levels) {
339 if (levels == 0)
340 levels = 1;
351 levels, levels == 1 ? "" : "s", nkeys);
  /src/lib/libkvm/
kvm_aarch64.c 116 /* how many levels of page tables do we have? */
117 u_int levels = howmany(inputsz - page_shift, pte_shift); local
122 u_int addr_shift = page_shift + (levels - 1) * pte_shift;
155 if (--levels == 0) {
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/allwinner/
sun5i-a13-utoo-p66.dts 71 /* Note levels of 10 / 20% result in backlight off */
72 brightness-levels = <0 30 40 50 60 70 80 90 100>;
  /src/tests/usr.bin/indent/
t_misc.sh 176 warning: Standard Input:5: Reached internal limit of 20 struct levels
177 warning: Standard Input:6: Reached internal limit of 20 struct levels
178 warning: Standard Input:6: Reached internal limit of 20 struct levels
179 warning: Standard Input:6: Reached internal limit of 20 struct levels
180 warning: Standard Input:6: Reached internal limit of 20 struct levels
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imx53-tx53-x13x.dts 66 brightness-levels = <
86 brightness-levels = <
imx6qdl-tx6-lvds.dtsi 53 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
71 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
  /src/sys/arch/arm/footbridge/
footbridge_irqhandler.c 117 int levels = 0; local
121 levels |= (1U << ih->ih_ipl);
123 iq->iq_levels = levels;
  /src/sys/arch/arm/xscale/
becc_icu.c 173 int levels = 0; local
178 levels |= (1U << ih->ih_ipl);
179 iq->iq_levels = levels;
ixp425_intr.c 198 int levels = 0; local
203 levels |= (1U << ih->ih_ipl);
204 iq->iq_levels = levels;
  /src/sys/arch/evbarm/ifpga/
ifpga_intr.c 149 int levels = 0; local
154 levels |= (1U << ih->ih_ipl);
155 iq->iq_levels = levels;
  /src/sys/arch/shark/isa/
isa_irqhandler.c 122 * Setup the irqmasks for the different Interrupt Priority Levels
277 /* First, figure out which levels each IRQ uses. */
279 int levels = 0; local
281 levels |= 1 << ptr->ih_level;
282 irqlevel[irq] = levels;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c 2420 smc_state->levels[0].dpm2.MaxPS = 0;
2421 smc_state->levels[0].dpm2.NearTDPDec = 0;
2422 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2423 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2424 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2473 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2474 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2475 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2476 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2477 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio)
3871 u32 levels = ps->performance_level_count; local
    [all...]

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