| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_ddi.c | 1558 int link_clock; local in function:icl_ddi_clock_get
1561 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1567 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1569 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1572 pipe_config->port_clock = link_clock;
1582 int link_clock; local in function:cnl_ddi_clock_get
1585 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1587 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1589 switch (link_clock) {
1591 link_clock = 81000
1630 int link_clock; local in function:skl_ddi_clock_get
1677 int link_clock = 0; local in function:hsw_ddi_clock_get
[all...] |
| intel_display.h | 495 int pixel_clock, int link_clock,
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| intel_dp.c | 513 u32 link_clock, u32 lane_count,
525 bits_per_pixel = (link_clock * lane_count * 8) /
2014 int mode_rate, link_clock, link_avail; local in function:intel_dp_compute_link_config_wide
2026 link_clock = intel_dp->common_rates[clock];
2027 link_avail = intel_dp_max_data_rate(link_clock,
2033 pipe_config->port_clock = link_clock;
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| intel_display.c | 7982 int pixel_clock, int link_clock,
7993 link_clock * nlanes * 8,
7997 compute_m_n(pixel_clock, link_clock,
11985 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11987 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11990 * link_clock = (m * link_clock) / n
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