| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_link_training.c | 141 u8 link_config[2]; local in function:intel_dp_link_training_clock_recovery
156 link_config[0] = link_bw;
157 link_config[1] = intel_dp->lane_count;
159 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
160 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
167 link_config[0] = 0;
168 link_config[1] = DP_SET_ANSI_8B10B;
169 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
|
| /src/sys/dev/pci/cxgb/ |
| cxgb_main.c | 919 t3_link_start(&pi->phy, mac, &pi->link_config);
982 t3_link_start(&p->phy, mac, &p->link_config);
1222 ifp->if_baudrate = p->link_config.speed * 1000000;
1380 if (!p->link_config.link_ok)
1521 if (!p->link_config.link_ok)
1526 switch (p->link_config.speed) {
1538 if (p->link_config.duplex)
1589 p->ifp->if_baudrate = p->link_config.speed * 1000000;
1619 t3_link_start(&p->phy, mac, &p->link_config);
|
| cxgb_adapter.h | 110 struct link_config link_config; member in struct:port_info
|
| cxgb_common.h | 419 struct link_config { struct
661 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
|
| cxgb_t3_hw.c | 1115 struct link_config *lc = &pi->link_config;
1156 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
3547 static void __devinit init_link_config(struct link_config *lc,
3794 init_link_config(&p->link_config, p->port_type->caps);
|
| /src/sys/dev/pci/ |
| mpiireg.h | 1252 u_int8_t link_config; member in struct:mpii_cfg_fc_port_pg1
|
