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    Searched refs:loadInputValue (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.h 93 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
96 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
AMDGPUCallLowering.cpp 800 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
850 LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
856 LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
865 LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
880 LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
AMDGPUISelLowering.h 309 SDValue loadInputValue(SelectionDAG &DAG,
AMDGPULegalizerInfo.cpp 1769 if (!loadInputValue(QueuePtr, B, AMDGPUFunctionArgInfo::QUEUE_PTR))
2720 bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
2751 bool AMDGPULegalizerInfo::loadInputValue(
2762 return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy);
2768 if (!loadInputValue(MI.getOperand(0).getReg(), B, ArgType))
3486 if (!loadInputValue(KernargPtrReg, B,
4566 if (!loadInputValue(LiveIn, B, AMDGPUFunctionArgInfo::QUEUE_PTR))
SIISelLowering.cpp 2742 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2792 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2795 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2803 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2817 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
6535 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
6539 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
6543 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
AMDGPUISelLowering.cpp 4166 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,

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