| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_reg.c | 50 uint32_t mask1, uint32_t field_value1,
57 set_reg_field_value_masks(field_value_mask, field_value1, mask1,
78 uint32_t mask1, uint32_t field_value1, ...)
85 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
95 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...)
101 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
|
| dmub_reg.h | 118 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
121 uint32_t mask1, uint32_t field_value1, ...);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| amdgpu_dc_helper.c | 133 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
141 field_value1, mask1, shift1);
250 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
259 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
278 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
286 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
340 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
344 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
350 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
355 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1)
[all...] |
| dm_services.h | 141 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
145 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
113 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
115 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
116 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/netatalk/ |
| at_control.c | 713 u_int mask1; local in function:aa_dorangeroute
732 mask1 = 1;
733 while (((bot & ~mask1) >= bot)
734 && ((bot | mask1) <= top)) {
735 mask1 <<= 1;
736 mask1 |= 1;
738 mask1 >>= 1;
739 mask.s_net = htons(~mask1);
750 bot = (bot | mask1) + 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 397 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
401 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
406 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
412 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
419 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
427 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
436 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
494 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
500 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
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| /src/sys/dev/pci/ |
| pci_map.c | 116 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; local in function:pci_mem_find
166 mask1 = pci_conf_read(pc, tag, reg + 4);
197 wmask = (uint64_t)mask1 << 32UL | mask;
218 (address1 != 0 || mask1 != 0xffffffff)) {
|
| /src/sys/net/npf/ |
| npf_inet.c | 208 npf_addr_cmp(const npf_addr_t *addr1, const npf_netmask_t mask1,
213 if (mask1 != NPF_NO_NETMASK) {
214 npf_addr_mask(addr1, mask1, alen, &realaddr1);
|
| /src/sys/dev/rasops/ |
| rasops.c | 1049 uint32_t mask1, mask2, *dp; local in function:rasops_do_cursor
1113 mask1 = rasops_lmask32[4 - slop1];
1120 *dp = *dp ^ mask1;
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