| /src/sys/external/isc/atheros_hal/dist/ar5212/ |
| ar5212_interrupts.c | 58 uint32_t mask2; local in function:ar5212GetPendingInterrupts
62 mask2 = 0;
67 mask2 |= HAL_INT_TIM;
69 mask2 |= HAL_INT_DTIM;
71 mask2 |= HAL_INT_DTIMSYNC;
73 mask2 |= HAL_INT_CABEND;
75 mask2 |= HAL_INT_TBTT;
109 *masked |= mask2;
143 uint32_t mask, mask2; local in function:ar5212SetInterrupts
155 mask2 = 0
[all...] |
| /src/sys/external/isc/atheros_hal/dist/ar5416/ |
| ar5416_interrupts.c | 84 uint32_t mask2; local in function:ar5416GetPendingInterrupts
86 mask2 = 0;
90 mask2 |= HAL_INT_TIM;
92 mask2 |= HAL_INT_DTIM;
94 mask2 |= HAL_INT_DTIMSYNC;
96 mask2 |= HAL_INT_CABEND;
98 mask2 |= HAL_INT_GTT;
100 mask2 |= HAL_INT_CST;
102 mask2 |= HAL_INT_TSFOOR;
138 *masked |= mask2;
178 uint32_t mask, mask2; local in function:ar5416SetInterrupts
[all...] |
| /src/sys/arch/hpcmips/vr/ |
| vrc4172gpio.c | 392 u_int32_t mask, mask2; local in function:vrc4172gpio_intr_dump
396 mask2 = (1 << (port % 8));
406 if (read_4(sc, intlv_reg) & (mask2 << 8)) {
409 if (read_4(sc, intlv_reg) & mask2)
415 if (read_4(sc, intlv_reg) & mask2)
484 u_int32_t reg, mask, mask2; local in function:vrc4172gpio_intr_establish
498 mask2 = (1 << (port % 8));
536 reg &= ~(mask2 << 8);
537 reg |= mask2;
540 reg &= ~(mask2 << 8)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| amdgpu_dc_helper.c | 341 uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
345 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
351 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
356 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
363 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
369 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
377 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
384 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
393 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
401 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
120 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
122 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 398 uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
402 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
407 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
413 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
420 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
428 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
437 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
|
| /src/sys/net/npf/ |
| npf_inet.c | 209 const npf_addr_t *addr2, const npf_netmask_t mask2, const int alen)
217 if (mask2 != NPF_NO_NETMASK) {
218 npf_addr_mask(addr2, mask2, alen, &realaddr2);
|
| /src/sys/dev/rasops/ |
| rasops.c | 1049 uint32_t mask1, mask2, *dp; local in function:rasops_do_cursor
1114 mask2 = rasops_rmask32[slop2];
1130 *dp = *dp ^ mask2;
|
| /src/sys/dev/ic/ |
| athn.c | 2114 uint32_t mask2; local in function:athn_enable_interrupts
2120 mask2 = AR_READ(sc, AR_IMR_S2);
2121 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2123 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST;
2124 AR_WRITE(sc, AR_IMR_S2, mask2);
|
