| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| mmsch_v1_0.h | 83 uint32_t mask_value; member in struct:mmsch_v1_0_cmd_direct_read_modify_write
88 uint32_t mask_value; member in struct:mmsch_v1_0_cmd_direct_polling
117 direct_rd_mod_wt->mask_value = mask;
129 direct_poll->mask_value = mask;
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pci/ |
| nouveau_nvkm_subdev_pci_g84.c | 88 u32 mask_value; local
91 mask_value = 0x20;
93 mask_value = 0x10;
95 nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
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| nouveau_nvkm_subdev_pci_gk104.c | 135 u32 mask_value; local
139 mask_value = 0x00000;
142 mask_value = 0x40000;
146 mask_value = 0x80000;
150 nvkm_mask(device, 0x8c040, 0xc0000, mask_value);
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| /src/sys/external/bsd/ena-com/ |
| ena_com.c | 1625 u32 mask_value = 0; local
1628 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1630 ENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
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| /src/crypto/external/apache2/openssl/dist/ssl/quic/ |
| quic_impl.c | 1014 static uint64_t quic_mask_or_options(SSL *ssl, uint64_t mask_value, uint64_t or_value)
1029 hs_mask_value = (mask_value & OSSL_QUIC_PERMITTED_OPTIONS_CONN);
1037 = ((ctx.qc->default_ssl_options & ~mask_value) | or_value)
1044 = ((ctx.xso->ssl_options & ~mask_value) | or_value)
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ci_dpm.c | 2619 u32 mask_value = 0; local
2622 mask_value = mask_value << 1;
2624 mask_value |= 0x1;
2626 mask_value &= 0xFFFFFFFE;
2629 return mask_value;
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| /src/external/gpl3/gdb.old/dist/gdb/ |
| breakpoint.c | 10404 struct value *mask_value;
10412 mask_value = parse_to_comma_and_eval (&value_start);
10413 mask = value_as_address (mask_value);
10396 struct value *mask_value; local
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| /src/external/gpl3/gdb/dist/gdb/ |
| breakpoint.c | 10433 struct value *mask_value;
10441 mask_value = parse_to_comma_and_eval (&value_start);
10442 mask = value_as_address (mask_value);
10425 struct value *mask_value; local
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