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    Searched refs:masks (Results 1 - 25 of 74) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
hw_ddc.h 37 const struct ddc_sh_mask *masks; member in struct:hw_ddc
hw_generic.h 38 const struct generic_sh_mask *masks; member in struct:hw_generic
hw_hpd.h 37 const struct hpd_sh_mask *masks; member in struct:hw_hpd
amdgpu_hw_generic.c 45 generic->shifts->field_name, generic->masks->field_name
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_hw.c 46 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
85 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK)
87 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT)
89 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED)
91 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE)
283 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
604 const struct dce_i2c_mask *masks)
611 dce_i2c_hw->masks = masks;
627 const struct dce_i2c_mask *masks)
    [all...]
amdgpu_dce_hwseq.c 43 hws->shifts->field_name, hws->masks->field_name
80 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
125 if (hws->masks->BLND_ALPHA_MODE != 0) {
dce_i2c_hw.h 275 const struct dce_i2c_mask *masks; member in struct:dce_i2c_hw
284 const struct dce_i2c_mask *masks);
292 const struct dce_i2c_mask *masks);
300 const struct dce_i2c_mask *masks);
308 const struct dce_i2c_mask *masks);
316 const struct dce_i2c_mask *masks);
dce_audio.h 130 const struct dce_audio_mask *masks; member in struct:dce_audio
138 const struct dce_audio_mask *masks);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_cm_common.h 73 struct xfer_func_mask masks; member in struct:xfer_func_reg
88 struct cm_color_matrix_mask masks; member in struct:color_matrices_reg
amdgpu_dcn10_dpp_cm.c 124 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
126 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
219 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
221 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
266 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
268 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
270 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
272 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
275 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
277 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/via/
via_irq.c 224 maskarray_t *masks; local in function:via_driver_irq_wait
247 masks = dev_priv->irq_masks;
252 if (masks[real_irq][2] && !force_sequence) {
255 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
256 masks[irq][4]));
266 if (masks[real_irq][2] && !force_sequence) {
268 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
269 masks[irq][4]))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mpc.c 171 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
173 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
229 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
231 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
257 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
259 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
261 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
263 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
265 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
267 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B
    [all...]
amdgpu_dcn20_vmid.c 44 vmid->shifts->field_name, vmid->masks->field_name
dcn20_vmid.h 87 const struct dcn20_vmid_mask *masks; member in struct:dcn20_vmid
amdgpu_dcn20_dpp_cm.c 195 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
197 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
290 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
292 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
368 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
370 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
372 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
374 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
377 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
379 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
amdgpu_hw_factory_dcn10.c 162 generic->masks = &generic_mask[en];
187 ddc->masks = &ddc_mask;
197 hpd->masks = &hpd_mask;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 205 ddc->masks = &ddc_mask[en];
215 hpd->masks = &hpd_mask;
225 generic->masks = &generic_mask[en];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_factory_dcn21.c 170 generic->masks = &generic_mask[en];
195 ddc->masks = &ddc_mask[en];
205 hpd->masks = &hpd_mask;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/
amdgpu_hw_factory_dce110.c 142 ddc->masks = &ddc_mask;
152 hpd->masks = &hpd_mask;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/
amdgpu_hw_factory_dce80.c 142 ddc->masks = &ddc_mask;
152 hpd->masks = &hpd_mask;
  /src/sys/arch/dreamcast/dreamcast/
sysasic.c 209 volatile uint32_t *masks, *stats; local in function:sysasic_intr_enable
224 masks = (volatile uint32_t *) SYSASIC_INTR_EN(syh->syh_idx);
237 masks[evmap] = syh->syh_events[evmap];
240 masks[evmap] = syh->syh_events[evmap] & ~evbit;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
amdgpu_hw_factory_dce120.c 155 ddc->masks = &ddc_mask;
165 hpd->masks = &hpd_mask;
  /src/sys/dev/pci/
hifn7751reg.h 80 * Masks for the "length" field of struct hifn_desc.
373 volatile u_int16_t masks; member in struct:hifn_base_command
395 volatile u_int16_t masks; member in struct:hifn_crypt_command
425 volatile u_int16_t masks; member in struct:hifn_mac_command
453 volatile u_int16_t masks; member in struct:hifn_comp_command
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hwseq.c 51 hws->shifts->field_name, hws->masks->field_name
  /src/sys/external/bsd/ipf/netinet/
radix_ipf.h 28 struct ipf_rdx_mask *masks; member in struct:ipf_rdx_node

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