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  /src/external/bsd/openldap/dist/libraries/liblunicode/ure/
urestubs.c 72 } masks[32] = { variable in typeref:struct:ucmaskmap
126 mask1 |= masks[i].mask1;
127 mask2 |= masks[i].mask2;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
hw_ddc.h 37 const struct ddc_sh_mask *masks; member in struct:hw_ddc
hw_generic.h 38 const struct generic_sh_mask *masks; member in struct:hw_generic
hw_hpd.h 37 const struct hpd_sh_mask *masks; member in struct:hw_hpd
  /src/external/bsd/pdisk/dist/
bitfield.c 47 const uint32_t masks[] = { variable
84 m = masks[length];
100 m = masks[length];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_i2c_hw.c 46 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
85 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK)
87 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT)
89 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED)
91 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE)
283 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
604 const struct dce_i2c_mask *masks)
611 dce_i2c_hw->masks = masks;
627 const struct dce_i2c_mask *masks)
    [all...]
amdgpu_dce_hwseq.c 43 hws->shifts->field_name, hws->masks->field_name
80 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
125 if (hws->masks->BLND_ALPHA_MODE != 0) {
dce_i2c_hw.h 275 const struct dce_i2c_mask *masks; member in struct:dce_i2c_hw
284 const struct dce_i2c_mask *masks);
292 const struct dce_i2c_mask *masks);
300 const struct dce_i2c_mask *masks);
308 const struct dce_i2c_mask *masks);
316 const struct dce_i2c_mask *masks);
dce_audio.h 130 const struct dce_audio_mask *masks; member in struct:dce_audio
138 const struct dce_audio_mask *masks);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_cm_common.h 73 struct xfer_func_mask masks; member in struct:xfer_func_reg
88 struct cm_color_matrix_mask masks; member in struct:color_matrices_reg
amdgpu_dcn10_dpp_cm.c 124 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
126 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
219 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
221 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
266 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
268 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
270 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
272 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
275 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
277 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B
    [all...]
  /src/external/cddl/osnet/dist/common/acl/
acl_common.c 957 /* check for invalid masks */
993 /* more detailed checking of masks */
1577 acl_trivial_access_masks(mode_t mode, boolean_t isdir, trivial_acl_t *masks)
1585 masks->deny1 = 0;
1587 masks->deny1 |= read_mask;
1589 masks->deny1 |= write_mask;
1591 masks->deny1 |= execute_mask;
1593 masks->deny2 = 0;
1595 masks->deny2 |= read_mask;
1597 masks->deny2 |= write_mask
1643 trivial_acl_t masks; local
    [all...]
acl_common.h 63 trivial_acl_t *masks);
  /src/external/bsd/openldap/dist/libraries/liblunicode/ucdata/
ucdata.c 79 * A simple array of 32-bit masks for lookup.
1305 int ucdata_load(char *paths, int masks) { return 0; }
1306 void ucdata_unload(int masks) { }
1307 int ucdata_reload(char *paths, int masks) { return 0; }
1313 ucdata_load(char *paths, int masks)
1317 if (masks & UCDATA_CTYPE)
1319 if (masks & UCDATA_CASE)
1321 if (masks & UCDATA_DECOMP)
1323 if (masks & UCDATA_CMBCL)
1325 if (masks & UCDATA_NUM
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/via/
via_irq.c 224 maskarray_t *masks; local
247 masks = dev_priv->irq_masks;
252 if (masks[real_irq][2] && !force_sequence) {
255 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
256 masks[irq][4]));
266 if (masks[real_irq][2] && !force_sequence) {
268 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
269 masks[irq][4]))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mpc.c 171 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
173 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
229 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
231 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
257 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
259 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
261 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
263 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
265 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
267 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B
    [all...]
amdgpu_dcn20_vmid.c 44 vmid->shifts->field_name, vmid->masks->field_name
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
amdgpu_hw_factory_dcn10.c 162 generic->masks = &generic_mask[en];
187 ddc->masks = &ddc_mask;
197 hpd->masks = &hpd_mask;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 205 ddc->masks = &ddc_mask[en];
215 hpd->masks = &hpd_mask;
225 generic->masks = &generic_mask[en];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_factory_dcn21.c 170 generic->masks = &generic_mask[en];
195 ddc->masks = &ddc_mask[en];
205 hpd->masks = &hpd_mask;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/
amdgpu_hw_factory_dce110.c 142 ddc->masks = &ddc_mask;
152 hpd->masks = &hpd_mask;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/
amdgpu_hw_factory_dce80.c 142 ddc->masks = &ddc_mask;
152 hpd->masks = &hpd_mask;
  /src/sys/arch/dreamcast/dreamcast/
sysasic.c 209 volatile uint32_t *masks, *stats; local
224 masks = (volatile uint32_t *) SYSASIC_INTR_EN(syh->syh_idx);
237 masks[evmap] = syh->syh_events[evmap];
240 masks[evmap] = syh->syh_events[evmap] & ~evbit;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
amdgpu_hw_factory_dce120.c 155 ddc->masks = &ddc_mask;
165 hpd->masks = &hpd_mask;
  /src/sys/dev/pci/
hifn7751reg.h 80 * Masks for the "length" field of struct hifn_desc.
373 volatile u_int16_t masks; member in struct:hifn_base_command
395 volatile u_int16_t masks; member in struct:hifn_crypt_command
425 volatile u_int16_t masks; member in struct:hifn_mac_command
453 volatile u_int16_t masks; member in struct:hifn_comp_command

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