| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_mcp77.c | 91 u32 mast = nvkm_rd32(device, 0x00c054); local in function:mcp77_clk_read
104 switch (mast & 0x000c0000) {
114 switch (mast & 0x00000003) {
122 if ((mast & 0x03000000) != 0x03000000)
125 if ((mast & 0x00000200) == 0x00000000)
128 switch (mast & 0x00000c00) {
136 switch (mast & 0x00000030) {
138 if (mast & 0x00000040)
152 switch (mast & 0x00400000) {
165 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
309 u32 pllmask = 0, mast; local in function:mcp77_clk_prog
[all...] |
| nouveau_nvkm_subdev_clk_nv50.c | 134 u32 src, mast = nvkm_rd32(device, 0x00c040); local in function:read_pll_ref
138 src = !!(mast & 0x00200000);
141 src = !!(mast & 0x00400000);
144 src = !!(mast & 0x00010000);
147 src = !!(mast & 0x02000000);
166 u32 mast = nvkm_rd32(device, 0x00c040); local in function:read_pll
173 if (base == 0x004028 && (mast & 0x00100000)) {
202 u32 mast = nvkm_rd32(device, 0x00c040); local in function:nv50_clk_read
217 switch (mast & 0x30000000) {
225 if (!(mast & 0x00100000)
[all...] |
| nouveau_nvkm_subdev_clk_nv40.c | 107 u32 mast = nvkm_rd32(device, 0x00c040); local in function:nv40_clk_read
115 return read_clk(clk, (mast & 0x00000003) >> 0);
117 return read_clk(clk, (mast & 0x00000030) >> 4);
124 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
|
