| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_dsc.h | 67 const uint32_t max_bpp,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| amdgpu_dc_dsc.c | 332 /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock
337 const uint32_t max_bpp,
346 range->max_kbps = dsc_div_by_10_round_up(max_bpp * timing->pix_clk_100hz);
347 range->max_target_bpp_x16 = max_bpp * 16;
878 /* If DSC is possbile, get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range and
886 const uint32_t max_bpp,
906 get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp.h | 36 int min_bpp, max_bpp; member in struct:link_config_limits
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| intel_psr.c | 620 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; local in function:intel_psr2_config_valid
644 max_bpp = 30;
648 max_bpp = 24;
652 max_bpp = 24;
662 if (crtc_state->pipe_bpp > max_bpp) {
664 crtc_state->pipe_bpp, max_bpp);
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| intel_dp_mst.c | 65 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
191 limits.max_bpp = min(pipe_config->pipe_bpp, 24);
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| intel_vbt_defs.h | 881 u8 max_bpp; /* mapping */ member in struct:dsc_compression_parameters_entry
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| intel_bios.c | 2444 VBT_DSC_MAX_BPP(dsc->max_bpp));
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| intel_dp.c | 1967 limits->min_bpp = limits->max_bpp = bpp;
2016 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2253 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2273 limits.max_bpp, adjusted_mode->crtc_clock);
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| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_main.c | 399 static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGBA8888 */ local in function:ast_mode_config_mode_valid
409 fbsize = mode->hdisplay * mode->vdisplay * max_bpp;
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