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    Searched refs:max_clks_state (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
amdgpu_dce_clk_mgr.c 212 for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
220 if (low_req_clk > clk_mgr_dce->max_clks_state) {
222 if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
226 low_req_clk = clk_mgr_dce->max_clks_state;
463 clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
465 clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr_internal.h 263 enum dm_pp_clocks_state max_clks_state; member in struct:clk_mgr_internal
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 231 for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
239 if (low_req_clk > clk_mgr_dce->max_clks_state) {
241 if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
245 low_req_clk = clk_mgr_dce->max_clks_state;
837 clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state;
839 clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;

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