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    Searched refs:maximum_number_of_surfaces (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dce_calcs.h 235 #define maximum_number_of_surfaces 12 macro
365 bool fbc_en[maximum_number_of_surfaces];
366 bool lpt_en[maximum_number_of_surfaces];
367 bool displays_match_flag[maximum_number_of_surfaces];
368 bool use_alpha[maximum_number_of_surfaces];
369 bool orthogonal_rotation[maximum_number_of_surfaces];
370 bool enable[maximum_number_of_surfaces];
371 bool access_one_channel_only[maximum_number_of_surfaces];
372 bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];
373 bool interlace_mode[maximum_number_of_surfaces];
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dce_calcs.c 114 enum bw_defines v_filter_init_mode[maximum_number_of_surfaces] __unused;
115 enum bw_defines tiling_mode[maximum_number_of_surfaces];
116 enum bw_defines surface_type[maximum_number_of_surfaces];
155 /* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
156 /* maximum_number_of_surfaces-1: d1 display_write_back420 chroma*/
296 for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {
354 data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0;
355 data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0;
357 data->enable[maximum_number_of_surfaces - 2] = 1;
358 data->enable[maximum_number_of_surfaces - 1] = 1
    [all...]
calcs_logger.h 384 for (i = 0; i < maximum_number_of_surfaces; i++) {
538 for (i = 0; i < maximum_number_of_surfaces; i++) {

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