| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm10.S | 42 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
46 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
74 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
75 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
|
| cpufunc_asm_arm1136.S | 40 mcr p15, 0, r0, c7, c10, 2 /* clean data cache line (via index) */
41 mcr p15, 0, r0, c7, c10, 5 /* data memory barrier */
42 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
|
| cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
53 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
59 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
64 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
67 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
76 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
|
| cpufunc_asm_arm8.S | 46 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
53 mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
58 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
83 mcr p15, 0, r0, c2, c0, 0
103 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
108 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
111 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
120 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
125 mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
133 mcr p15, 0, r2, c7, c11,
[all...] |
| cpufunc_asm_arm11.S | 50 mcr p15, 0, r0, c2, c0, 0 /* set the new TTBR0 */
71 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
72 mcr p15, 0, r0, c2, c0, 0 /* set the new TTBR0 */
77 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
93 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
94 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
103 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
106 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
110 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
116 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb *
[all...] |
| cpufunc_asm_arm67.S | 56 mcr p15, 0, r0, c2, c0, 0
74 mcr p15, 0, r0, c5, c0, 0
78 mcr p15, 0, r0, c6, c0, 0
85 mcr p15, 0, r0, c7, c0, 0
96 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
99 mcr p15, 0, r0, c2, c0, 0
102 mcr p15, 0, r0, c5, c0, 0
106 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
|
| cpufunc_asm_arm11x6.S | 70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
105 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
106 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
110 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
114 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
135 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer *
[all...] |
| cpufunc_asm_armv6.S | 57 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
85 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
86 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
104 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
118 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
128 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
139 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache *
[all...] |
| cpufunc_asm_sa1.S | 67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
72 mcr p15, 0, r0, c2, c0, 0
95 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
99 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
100 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
109 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
114 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
119 mcr p15, 0, r0, c7, c6, 0 /* flush D cache *
[all...] |
| cpufunc_asm_xscale.S | 150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
151 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
159 mcr p15, 0, r0, c2, c0, 0
164 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
187 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
188 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
191 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
192 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
201 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache *
[all...] |
| cpufunc_asm_arm9.S | 53 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
63 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
64 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
67 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
68 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
116 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
120 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index *
[all...] |
| cpufunc_asm_armv5.S | 55 1: mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
79 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
80 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
131 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer *
[all...] |
| cpufunc_asm_sa11x0.S | 89 mcr p15, 0, r0, c15, c2, 2 /* disable clock switching */
91 mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt
93 mcr p15, 0, r0, c15, c1, 2 /* re-enable clock switching */
113 mcr p15, 0, r0, c2, c0, 0
116 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
124 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
|
| cpufunc_asm_arm7tdmi.S | 63 mcr p15, 0, r1, c2, c0, 0
83 mcr p15, 0, r0, c8, c7, 0
88 mcr p15, 0, r0, c8, c7, 1
91 mcr p15, 0, r0, c8, c7, 1
102 mcr p15, 0, r0, c7, c7, 0
|
| cpufunc_asm_armv5_ec.S | 64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
67 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
70 1: mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
112 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
129 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
133 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer *
[all...] |
| cpufunc_asm_ixp12x0.S | 54 mcr p15, 0, r0, c2, c0, 0
57 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
66 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
|
| /src/sys/arch/vax/vax/ |
| ka780.c | 137 #define M780C_INH(mcr) \
138 ((mcr)->mc_reg[2] = (M780_ICRD|M780_HIER|M780_ERLOG)); \
140 #define M780C_ENA(mcr) \
141 ((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)); mtpr(3<<14, PR_SBIER);
142 #define M780C_ERR(mcr) \
143 ((mcr)->mc_reg[2] & (M780_ERLOG))
145 #define M780C_SYN(mcr) ((mcr)->mc_reg[2] & 0xff)
146 #define M780C_ADDR(mcr) (((mcr)->mc_reg[2] >> 8) & 0xfffff
176 struct mcr780 * const mcr = (void *)sa->sa_ioh; \/* XXX *\/ local in function:mem_sbi_attach
257 struct mcr780 *mcr; local in function:ka780_memerr
[all...] |
| ka750.c | 158 #define M750_INH(mcr) ((mcr)->mc_inh = 0)
159 #define M750_ENA(mcr) ((mcr)->mc_err = (M750_UNCORR|M750_CORERR), \
160 (mcr)->mc_inh = M750_ICRD)
161 #define M750_ERR(mcr) ((mcr)->mc_err & (M750_UNCORR|M750_CORERR))
171 struct mcr750 * const mcr = (struct mcr750 *)sa->sa_ioh; local in function:ka750_memenable
177 cardinfo = mcr->mc_inf;
221 struct mcr750 * const mcr = (struct mcr750 *)mcraddr[0] local in function:ka750_memerr
[all...] |
| /src/sys/arch/evbarm/ixm1200/ |
| ixm1200_start.S | 72 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */
80 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
84 mcr p15, 0, r0, c3, c0 ,0 /* write domain */
91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
94 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */
95 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */
99 mcr p15, 0, r0, c13, c0 ,0 /* process ID 0
103 mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */
104 mcr p15, 0, r0, c15, c1 ,0 /* DBVR = 0 *
[all...] |
| /src/sys/arch/evbarm/iq80310/ |
| iq80310_start.S | 55 mcr p15, 0, r2, c1, c0, 0
113 mcr p15, 0, r0, c2, c0, 0
116 mcr p15, 0, r0, c8, c7, 0
120 mcr p15, 0, r0, c3, c0, 0
128 mcr p15, 0, r2, c1, c0, 0
|
| /src/common/dist/zlib/contrib/minizip/ |
| make_vms.com | 20 $ mcr []minizip test minizip_info.txt
21 $ mcr []miniunz -l test.zip
23 $ mcr []miniunz test.zip
|
| /src/sys/arch/evbarm/armadaxp/ |
| armadaxp_start.S | 77 mcr p15, 0, r2, c1, c0, 0
101 mcr p15, 0, r0, c2, c0, 0 // Set TTBR0
103 mcr p15, 0, r0, c2, c0, 1 // Set TTBR1
108 mcr p15, 0, r0, c2, c0, 2 // TTBCR write
111 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
113 mcr p15, 0, r0, c13, c0, 1 // CONTEXTIDR write: Set ASID to 0
117 mcr p15, 0, r0, c3, c0, 0 // DACR write
129 mcr p15, 0, r0, c1, c0, 0
|
| /src/sys/arch/shark/stand/ofwboot/ |
| srt0.S | 71 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
72 mcr p15, 0, r0, c7, c5, 0 /* flush I$ */
|
| /src/sys/arch/evbarm/imx31/ |
| imx31lk_start.S | 59 mcr p15, 0, r0, c2, c0, 1 /* copy it to TTBR1 */
61 mcr p15, 0, r3, c2, c0, 2 /* set TTBCR to enable TTBR1 */
91 mcr p15, 0, r0, c3, c0, 0
100 mcr p15, 0, r0, c8, c7, 0
|
| /src/sys/arch/netwinder/netwinder/ |
| nwmmu.S | 102 mcr p15, 0, r0, c2, c0, 0
105 mcr p15, 0, r0, c8, c7, 0
109 mcr p15, 0, r0, c3, c0, 0
114 mcr p15, 0, r2, c1, c0, 0
|
