| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm67.S | 53 mcrne p15, 0, r2, c7, c0, 0
59 mcrne p15, 0, r0, c5, c0, 0
62 mcrne p15, 0, r0, c7, c0, 0
|
| cpufunc_asm_armv6.S | 52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
53 mcrne p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain the write buffer */
59 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| cpufunc_asm_arm11.S | 54 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
|
| cpufunc_asm.S | 131 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
|
| cpufunc_asm_arm8.S | 80 mcrne p15, 0, r0, c7, c7, 0 /* flush I+D cache */
86 mcrne p15, 0, r0, c8, c7, 0
89 mcrne p15, 0, r0, c7, c7, 0
|
| cpufunc_asm_sa1.S | 75 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
|
| cpufunc_asm_xscale.S | 122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
123 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
|
| cpufunc_asm_arm9.S | 55 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| cpufunc_asm_armv5.S | 56 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| cpufunc_asm_armv5_ec.S | 71 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| /src/sys/arch/acorn32/stand/boot32/ |
| start.S | 81 mcrne p15, 0, r0, c7, c7, 0 /* flush v4 ID cache */
82 mcrne p15, 0, r0, c7, c10, 4 /* drain WB (v4) */
96 /*1*/ mcrne p15, 0, r1, c7, c5, 0 /* write zero in ARMv4 MMU disable */ label
136 mcrne p15, 0, r0, c7, c7, 0 /* flush v4 ID cache */
141 mcrne p15, 0, r0, c7, c10, 4 /* drain WB (v4) */
|
