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    Searched refs:memVT (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 2215 EVT MemVT = Load->getMemoryVT();
2217 MemVT, *Load->getMemOperand())) {
3445 // memVT is bogus. These intrinsics have IntrInaccessibleMemOnly attribute
3448 Info.memVT = MVT::i1;
3478 Info.memVT = MVT::v8f16;
3502 Info.memVT = MVT::v2i32;
3528 Info.memVT = MVT::v4i32;
3566 Info.memVT = MVT::i32;
3587 Info.memVT = MVT::v4f16;
3608 Info.memVT = MVT::v8f32
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 707 Info.memVT = MVT::i32;
721 Info.memVT = MVT::i32;
729 Info.memVT = MVT::i64;
738 Info.memVT = Intrinsic == Intrinsic::wasm_load32_zero ? MVT::i32 : MVT::i64;
752 MVT MemVT;
756 MemVT = MVT::i8;
760 MemVT = MVT::i16;
764 MemVT = MVT::i32;
768 MemVT = MVT::i64;
784 Info.memVT = MemVT
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 1007 // correct memVT.
1056 Info.memVT = memVTFromImageReturn(CI.getType(), DMaskLanes);
1058 Info.memVT = EVT::getEVT(CI.getType());
1070 Info.memVT = memVTFromImageData(DataTy, DMaskLanes);
1072 Info.memVT = EVT::getEVT(DataTy);
1079 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
1099 Info.memVT = MVT::getVT(CI.getType());
1114 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
1129 Info.memVT = MVT::getVT(CI.getType());
1142 Info.memVT = MVT::getVT(CI.getType())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 2031 Info.memVT = MVT::getVT(ElTy);
2037 Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont));
2056 Info.memVT = MVT::getVT(VecTy);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 9490 EVT MemVT = LD->getMemoryVT();
9491 assert((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemVT == MVT::v16i1) &&
9493 assert(MemVT == Op.getValueType());
9511 EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()),
9517 DAG.getConstant(32 - MemVT.getSizeInBits(), dl, MVT::i32));
9519 if (MemVT != MVT::v16i1)
9520 Pred = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MemVT, Pred,
9528 EVT MemVT = LD->getMemoryVT()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
IRTranslator.cpp 2340 DL->getABITypeAlign(Info.memVT.getTypeForEVT(F->getContext())));
2342 uint64_t Size = Info.memVT.getStoreSize();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 4181 void selectGatherScatterAddrMode(SDValue &BasePtr, SDValue &Index, EVT MemVT,
4209 unsigned ScalarSizeInBytes = MemVT.getScalarSizeInBits() / 8;
4249 EVT MemVT = MGT->getMemoryVT();
4250 SDValue InputVT = DAG.getValueType(MemVT);
4260 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger());
4269 selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode,
4309 EVT MemVT = MSC->getMemoryVT();
4310 SDValue InputVT = DAG.getValueType(MemVT);
4320 InputVT = DAG.getValueType(MemVT.changeVectorElementTypeToInteger());
4327 selectGatherScatterAddrMode(BasePtr, Index, MemVT, Opcode
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 574 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
583 virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
587 /// Returns if it's reasonable to merge stores to MemVT size.
588 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
984 EVT memVT; // memory VT
991 // (taken from memVT if zero)
1221 EVT MemVT) const {
1222 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1224 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1232 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 5140 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5148 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5156 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48);
5164 Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64);
5187 Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements());
5200 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5212 Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts);
5398 bool X86TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
5407 return (MemVT.getSizeInBits() <= MaxIntSize);
5411 if (MemVT.getSizeInBits() > Subtarget.getPreferVectorWidth()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 2885 EVT MemVT = LD->getMemoryVT();
2886 if (!MemVT.isSimple())
2888 switch(MemVT.getSimpleVT().SimpleTy) {
8156 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
8180 if (LD->getMemoryVT() != MemVT)
10441 EVT MemVT = AtomicNode->getMemoryVT();
10442 if (MemVT.getSizeInBits() >= 32)
10447 auto HighBits = APInt::getHighBitsSet(32, 32 - MemVT.getSizeInBits());
10452 unsigned MaskVal = (1 << MemVT.getSizeInBits()) - 1;
10465 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 2453 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType());
2472 if (CondLHS.getValueType() != MemVT) {
2473 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT);
2474 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT);
3196 EVT MemVT =
3202 if (Op1.getValueType() != MemVT) {
3203 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT);
3204 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
4579 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
4580 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 852 Info.memVT = MVT::getVT(PtrTy->getElementType());
919 EVT MemVT = LD->getMemoryVT();
920 if ((MemVT == MVT::i8 || MemVT == MVT::i16 ||
921 (Subtarget.is64Bit() && MemVT == MVT::i32)) &&

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