1 /* $NetBSD: kfd_pm4_headers_vi.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef F32_MES_PM4_PACKETS_H 27 #define F32_MES_PM4_PACKETS_H 28 29 #ifndef PM4_MES_HEADER_DEFINED 30 #define PM4_MES_HEADER_DEFINED 31 union PM4_MES_TYPE_3_HEADER { 32 struct { 33 uint32_t reserved1 : 8; /* < reserved */ 34 uint32_t opcode : 8; /* < IT opcode */ 35 uint32_t count : 14;/* < Number of DWORDS - 1 in the 36 * information body 37 */ 38 uint32_t type : 2; /* < packet identifier 39 * It should be 3 for type 3 packets 40 */ 41 }; 42 uint32_t u32All; 43 }; 44 #endif /* PM4_MES_HEADER_DEFINED */ 45 46 /*--------------------MES_SET_RESOURCES--------------------*/ 47 48 #ifndef PM4_MES_SET_RESOURCES_DEFINED 49 #define PM4_MES_SET_RESOURCES_DEFINED 50 enum mes_set_resources_queue_type_enum { 51 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, 52 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, 53 queue_type__mes_set_resources__hsa_debug_interface_queue = 4 54 }; 55 56 57 struct pm4_mes_set_resources { 58 union { 59 union PM4_MES_TYPE_3_HEADER header; /* header */ 60 uint32_t ordinal1; 61 }; 62 63 union { 64 struct { 65 uint32_t vmid_mask:16; 66 uint32_t unmap_latency:8; 67 uint32_t reserved1:5; 68 enum mes_set_resources_queue_type_enum queue_type:3; 69 } bitfields2; 70 uint32_t ordinal2; 71 }; 72 73 uint32_t queue_mask_lo; 74 uint32_t queue_mask_hi; 75 uint32_t gws_mask_lo; 76 uint32_t gws_mask_hi; 77 78 union { 79 struct { 80 uint32_t oac_mask:16; 81 uint32_t reserved2:16; 82 } bitfields7; 83 uint32_t ordinal7; 84 }; 85 86 union { 87 struct { 88 uint32_t gds_heap_base:6; 89 uint32_t reserved3:5; 90 uint32_t gds_heap_size:6; 91 uint32_t reserved4:15; 92 } bitfields8; 93 uint32_t ordinal8; 94 }; 95 96 }; 97 #endif 98 99 /*--------------------MES_RUN_LIST--------------------*/ 100 101 #ifndef PM4_MES_RUN_LIST_DEFINED 102 #define PM4_MES_RUN_LIST_DEFINED 103 104 struct pm4_mes_runlist { 105 union { 106 union PM4_MES_TYPE_3_HEADER header; /* header */ 107 uint32_t ordinal1; 108 }; 109 110 union { 111 struct { 112 uint32_t reserved1:2; 113 uint32_t ib_base_lo:30; 114 } bitfields2; 115 uint32_t ordinal2; 116 }; 117 118 union { 119 struct { 120 uint32_t ib_base_hi:16; 121 uint32_t reserved2:16; 122 } bitfields3; 123 uint32_t ordinal3; 124 }; 125 126 union { 127 struct { 128 uint32_t ib_size:20; 129 uint32_t chain:1; 130 uint32_t offload_polling:1; 131 uint32_t reserved2:1; 132 uint32_t valid:1; 133 uint32_t process_cnt:4; 134 uint32_t reserved3:4; 135 } bitfields4; 136 uint32_t ordinal4; 137 }; 138 139 }; 140 #endif 141 142 /*--------------------MES_MAP_PROCESS--------------------*/ 143 144 #ifndef PM4_MES_MAP_PROCESS_DEFINED 145 #define PM4_MES_MAP_PROCESS_DEFINED 146 147 struct pm4_mes_map_process { 148 union { 149 union PM4_MES_TYPE_3_HEADER header; /* header */ 150 uint32_t ordinal1; 151 }; 152 153 union { 154 struct { 155 uint32_t pasid:16; 156 uint32_t reserved1:8; 157 uint32_t diq_enable:1; 158 uint32_t process_quantum:7; 159 } bitfields2; 160 uint32_t ordinal2; 161 }; 162 163 union { 164 struct { 165 uint32_t page_table_base:28; 166 uint32_t reserved3:4; 167 } bitfields3; 168 uint32_t ordinal3; 169 }; 170 171 uint32_t reserved; 172 173 uint32_t sh_mem_bases; 174 uint32_t sh_mem_config; 175 uint32_t sh_mem_ape1_base; 176 uint32_t sh_mem_ape1_limit; 177 178 uint32_t sh_hidden_private_base_vmid; 179 180 uint32_t reserved2; 181 uint32_t reserved3; 182 183 uint32_t gds_addr_lo; 184 uint32_t gds_addr_hi; 185 186 union { 187 struct { 188 uint32_t num_gws:6; 189 uint32_t reserved4:2; 190 uint32_t num_oac:4; 191 uint32_t reserved5:4; 192 uint32_t gds_size:6; 193 uint32_t num_queues:10; 194 } bitfields10; 195 uint32_t ordinal10; 196 }; 197 198 uint32_t completion_signal_lo; 199 uint32_t completion_signal_hi; 200 201 }; 202 203 #endif 204 205 /*--------------------MES_MAP_QUEUES--------------------*/ 206 207 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED 208 #define PM4_MES_MAP_QUEUES_VI_DEFINED 209 enum mes_map_queues_queue_sel_vi_enum { 210 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, 211 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 212 }; 213 214 enum mes_map_queues_queue_type_vi_enum { 215 queue_type__mes_map_queues__normal_compute_vi = 0, 216 queue_type__mes_map_queues__debug_interface_queue_vi = 1, 217 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, 218 queue_type__mes_map_queues__low_latency_static_queue_vi = 3 219 }; 220 221 enum mes_map_queues_engine_sel_vi_enum { 222 engine_sel__mes_map_queues__compute_vi = 0, 223 engine_sel__mes_map_queues__sdma0_vi = 2, 224 engine_sel__mes_map_queues__sdma1_vi = 3 225 }; 226 227 228 struct pm4_mes_map_queues { 229 union { 230 union PM4_MES_TYPE_3_HEADER header; /* header */ 231 uint32_t ordinal1; 232 }; 233 234 union { 235 struct { 236 uint32_t reserved1:4; 237 enum mes_map_queues_queue_sel_vi_enum queue_sel:2; 238 uint32_t reserved2:15; 239 enum mes_map_queues_queue_type_vi_enum queue_type:3; 240 uint32_t reserved3:2; 241 enum mes_map_queues_engine_sel_vi_enum engine_sel:3; 242 uint32_t num_queues:3; 243 } bitfields2; 244 uint32_t ordinal2; 245 }; 246 247 union { 248 struct { 249 uint32_t reserved3:1; 250 uint32_t check_disable:1; 251 uint32_t doorbell_offset:21; 252 uint32_t reserved4:3; 253 uint32_t queue:6; 254 } bitfields3; 255 uint32_t ordinal3; 256 }; 257 258 uint32_t mqd_addr_lo; 259 uint32_t mqd_addr_hi; 260 uint32_t wptr_addr_lo; 261 uint32_t wptr_addr_hi; 262 }; 263 #endif 264 265 /*--------------------MES_QUERY_STATUS--------------------*/ 266 267 #ifndef PM4_MES_QUERY_STATUS_DEFINED 268 #define PM4_MES_QUERY_STATUS_DEFINED 269 enum mes_query_status_interrupt_sel_enum { 270 interrupt_sel__mes_query_status__completion_status = 0, 271 interrupt_sel__mes_query_status__process_status = 1, 272 interrupt_sel__mes_query_status__queue_status = 2 273 }; 274 275 enum mes_query_status_command_enum { 276 command__mes_query_status__interrupt_only = 0, 277 command__mes_query_status__fence_only_immediate = 1, 278 command__mes_query_status__fence_only_after_write_ack = 2, 279 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 280 }; 281 282 enum mes_query_status_engine_sel_enum { 283 engine_sel__mes_query_status__compute = 0, 284 engine_sel__mes_query_status__sdma0_queue = 2, 285 engine_sel__mes_query_status__sdma1_queue = 3 286 }; 287 288 struct pm4_mes_query_status { 289 union { 290 union PM4_MES_TYPE_3_HEADER header; /* header */ 291 uint32_t ordinal1; 292 }; 293 294 union { 295 struct { 296 uint32_t context_id:28; 297 enum mes_query_status_interrupt_sel_enum 298 interrupt_sel:2; 299 enum mes_query_status_command_enum command:2; 300 } bitfields2; 301 uint32_t ordinal2; 302 }; 303 304 union { 305 struct { 306 uint32_t pasid:16; 307 uint32_t reserved1:16; 308 } bitfields3a; 309 struct { 310 uint32_t reserved2:2; 311 uint32_t doorbell_offset:21; 312 uint32_t reserved3:2; 313 enum mes_query_status_engine_sel_enum engine_sel:3; 314 uint32_t reserved4:4; 315 } bitfields3b; 316 uint32_t ordinal3; 317 }; 318 319 uint32_t addr_lo; 320 uint32_t addr_hi; 321 uint32_t data_lo; 322 uint32_t data_hi; 323 }; 324 #endif 325 326 /*--------------------MES_UNMAP_QUEUES--------------------*/ 327 328 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED 329 #define PM4_MES_UNMAP_QUEUES_DEFINED 330 enum mes_unmap_queues_action_enum { 331 action__mes_unmap_queues__preempt_queues = 0, 332 action__mes_unmap_queues__reset_queues = 1, 333 action__mes_unmap_queues__disable_process_queues = 2, 334 action__mes_unmap_queues__reserved = 3 335 }; 336 337 enum mes_unmap_queues_queue_sel_enum { 338 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, 339 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, 340 queue_sel__mes_unmap_queues__unmap_all_queues = 2, 341 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 342 }; 343 344 enum mes_unmap_queues_engine_sel_enum { 345 engine_sel__mes_unmap_queues__compute = 0, 346 engine_sel__mes_unmap_queues__sdma0 = 2, 347 engine_sel__mes_unmap_queues__sdmal = 3 348 }; 349 350 struct pm4_mes_unmap_queues { 351 union { 352 union PM4_MES_TYPE_3_HEADER header; /* header */ 353 uint32_t ordinal1; 354 }; 355 356 union { 357 struct { 358 enum mes_unmap_queues_action_enum action:2; 359 uint32_t reserved1:2; 360 enum mes_unmap_queues_queue_sel_enum queue_sel:2; 361 uint32_t reserved2:20; 362 enum mes_unmap_queues_engine_sel_enum engine_sel:3; 363 uint32_t num_queues:3; 364 } bitfields2; 365 uint32_t ordinal2; 366 }; 367 368 union { 369 struct { 370 uint32_t pasid:16; 371 uint32_t reserved3:16; 372 } bitfields3a; 373 struct { 374 uint32_t reserved4:2; 375 uint32_t doorbell_offset0:21; 376 uint32_t reserved5:9; 377 } bitfields3b; 378 uint32_t ordinal3; 379 }; 380 381 union { 382 struct { 383 uint32_t reserved6:2; 384 uint32_t doorbell_offset1:21; 385 uint32_t reserved7:9; 386 } bitfields4; 387 uint32_t ordinal4; 388 }; 389 390 union { 391 struct { 392 uint32_t reserved8:2; 393 uint32_t doorbell_offset2:21; 394 uint32_t reserved9:9; 395 } bitfields5; 396 uint32_t ordinal5; 397 }; 398 399 union { 400 struct { 401 uint32_t reserved10:2; 402 uint32_t doorbell_offset3:21; 403 uint32_t reserved11:9; 404 } bitfields6; 405 uint32_t ordinal6; 406 }; 407 }; 408 #endif 409 410 #ifndef PM4_MEC_RELEASE_MEM_DEFINED 411 #define PM4_MEC_RELEASE_MEM_DEFINED 412 enum RELEASE_MEM_event_index_enum { 413 event_index___release_mem__end_of_pipe = 5, 414 event_index___release_mem__shader_done = 6 415 }; 416 417 enum RELEASE_MEM_cache_policy_enum { 418 cache_policy___release_mem__lru = 0, 419 cache_policy___release_mem__stream = 1, 420 cache_policy___release_mem__bypass = 2 421 }; 422 423 enum RELEASE_MEM_dst_sel_enum { 424 dst_sel___release_mem__memory_controller = 0, 425 dst_sel___release_mem__tc_l2 = 1, 426 dst_sel___release_mem__queue_write_pointer_register = 2, 427 dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 428 }; 429 430 enum RELEASE_MEM_int_sel_enum { 431 int_sel___release_mem__none = 0, 432 int_sel___release_mem__send_interrupt_only = 1, 433 int_sel___release_mem__send_interrupt_after_write_confirm = 2, 434 int_sel___release_mem__send_data_after_write_confirm = 3 435 }; 436 437 enum RELEASE_MEM_data_sel_enum { 438 data_sel___release_mem__none = 0, 439 data_sel___release_mem__send_32_bit_low = 1, 440 data_sel___release_mem__send_64_bit_data = 2, 441 data_sel___release_mem__send_gpu_clock_counter = 3, 442 data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, 443 data_sel___release_mem__store_gds_data_to_memory = 5 444 }; 445 446 struct pm4_mec_release_mem { 447 union { 448 union PM4_MES_TYPE_3_HEADER header; /*header */ 449 unsigned int ordinal1; 450 }; 451 452 union { 453 struct { 454 unsigned int event_type:6; 455 unsigned int reserved1:2; 456 enum RELEASE_MEM_event_index_enum event_index:4; 457 unsigned int tcl1_vol_action_ena:1; 458 unsigned int tc_vol_action_ena:1; 459 unsigned int reserved2:1; 460 unsigned int tc_wb_action_ena:1; 461 unsigned int tcl1_action_ena:1; 462 unsigned int tc_action_ena:1; 463 unsigned int reserved3:6; 464 unsigned int atc:1; 465 enum RELEASE_MEM_cache_policy_enum cache_policy:2; 466 unsigned int reserved4:5; 467 } bitfields2; 468 unsigned int ordinal2; 469 }; 470 471 union { 472 struct { 473 unsigned int reserved5:16; 474 enum RELEASE_MEM_dst_sel_enum dst_sel:2; 475 unsigned int reserved6:6; 476 enum RELEASE_MEM_int_sel_enum int_sel:3; 477 unsigned int reserved7:2; 478 enum RELEASE_MEM_data_sel_enum data_sel:3; 479 } bitfields3; 480 unsigned int ordinal3; 481 }; 482 483 union { 484 struct { 485 unsigned int reserved8:2; 486 unsigned int address_lo_32b:30; 487 } bitfields4; 488 struct { 489 unsigned int reserved9:3; 490 unsigned int address_lo_64b:29; 491 } bitfields5; 492 unsigned int ordinal4; 493 }; 494 495 unsigned int address_hi; 496 497 unsigned int data_lo; 498 499 unsigned int data_hi; 500 }; 501 #endif 502 503 enum { 504 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 505 }; 506 507 #endif 508
Indexes created Tue Sep 30 11:09:46 GMT 2025