| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 143 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
152 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
379 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
388 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
416 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
417 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",
418 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 213 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
222 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
1235 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1245 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1278 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1287 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1316 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| dcn_calcs.h | 145 float meta_chunk_size; member in struct:dcn_bw_internal_vars
594 int meta_chunk_size; /*kbytes*/ member in struct:dcn_ip_params
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 170 dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs.meta_chunk_size);
|
| display_mode_structs.h | 497 unsigned int meta_chunk_size; member in struct:_vcs_dpi_display_data_rq_regs_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 226 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 219 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
223 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
|
| amdgpu_dcn10_hubp.c | 561 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
570 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
1043 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1053 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
|
| amdgpu_dcn10_hw_sequencer.c | 207 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
211 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
1793 "meta_chunk_size: %d \n"
1803 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 138 .meta_chunk_size = 2, /*kbytes*/
798 v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
1644 "meta_chunk_size: %d kbytes\n"
1678 dc->dcn_ip->meta_chunk_size,
1730 dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
|
| amdgpu_dcn_calc_auto.c | 795 v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i];
1323 v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0 / v->return_bw;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 184 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
|
| amdgpu_display_rq_dlg_calc_20v2.c | 184 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 161 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
|
