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    Searched refs:mfdcr (Results 1 - 21 of 21) sorted by relevancy

  /src/sys/arch/powerpc/ibm4xx/
ibm4xx_460ex_l2.c 88 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
118 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
184 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
188 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
191 while ((mfdcr(DCR_L2C0_SR) & L2C_SR_CC) == 0)
213 ibm4xx_460ex_l2_cfg = mfdcr(DCR_L2C0_CFG);
pic_uic.c 105 return mfdcr(DCR_EXISR);
111 return mfdcr(DCR_EXIER);
158 return mfdcr(DCR_UIC0_BASE + DCR_UIC_MSR);
164 return mfdcr(DCR_UIC0_BASE + DCR_UIC_ER);
216 return mfdcr(DCR_UIC1_BASE + DCR_UIC_MSR);
222 return mfdcr(DCR_UIC1_BASE + DCR_UIC_ER);
270 return mfdcr(DCR_UIC2_BASE + DCR_UIC_MSR);
276 return mfdcr(DCR_UIC2_BASE + DCR_UIC_ER);
326 return mfdcr(DCR_UIC3_BASE + DCR_UIC_MSR);
332 return mfdcr(DCR_UIC3_BASE + DCR_UIC_ER)
    [all...]
  /src/sys/arch/powerpc/include/ibm4xx/
cpu.h 100 mfdcr(const int reg) function
104 __asm volatile("mfdcr %0,%1" : "=r"(val) : "K"(reg));
119 return mfdcr(DCR_CPR0_CFGDATA);
133 return mfdcr(DCR_SDR0_CFGDATA);
  /src/sys/arch/evbppc/explora/
machdep.c 66 br[0] = mfdcr(DCR_BR4);
67 br[1] = mfdcr(DCR_BR5);
68 br[2] = mfdcr(DCR_BR6);
69 br[3] = mfdcr(DCR_BR7);
  /src/sys/arch/evbppc/obs405/
obs200_autoconf.c 58 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
obs266_autoconf.c 58 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
obs600_autoconf.c 103 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
obs200_machdep.c 130 pllmode = mfdcr(DCR_CPC0_PLLMR);
131 psr = mfdcr(DCR_CPC0_PSR);
  /src/sys/arch/evbppc/sam460ex/
autoconf.c 111 mfdcr(DCR_UIC1_BASE + DCR_UIC_PR) & ~0x80000000);
113 mfdcr(DCR_UIC1_BASE + DCR_UIC_TR) & ~0x80000000);
116 mfdcr(DCR_UIC3_BASE + DCR_UIC_PR) & ~0x000ff000);
118 mfdcr(DCR_UIC3_BASE + DCR_UIC_TR) & ~0x000ff000);
machdep.c 527 uint32_t cr = mfdcr(DCR_AHB_CR);
530 mfdcr(DCR_AHB_REV), mfdcr(DCR_AHB_TOP), mfdcr(DCR_AHB_BOT),
531 mfdcr(DCR_AHB_ATT), cr,
645 (unsigned int)mfdcr((base) + DCR_UIC_SR), \
646 (unsigned int)mfdcr((base) + DCR_UIC_MSR), \
647 (unsigned int)mfdcr((base) + DCR_UIC_ER), \
648 (unsigned int)mfdcr((base) + DCR_UIC_PR), \
649 (unsigned int)mfdcr((base) + DCR_UIC_TR)
    [all...]
  /src/sys/arch/evbppc/dht/
autoconf.c 66 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
machdep.c 148 val = mfdcr(DCR_SDRAM0_CFGDATA);
  /src/sys/arch/evbppc/virtex/
dcr.h 84 case (addr): val = mfdcr((base) + (addr) / 4); break
idcr.h 80 #define mfidcr(addr) mfdcr(IDCR_BASE + (addr))
  /src/sys/arch/evbppc/walnut/
autoconf.c 69 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
  /src/sys/arch/powerpc/ibm4xx/dev/
ecc_plb.c 150 esr = mfdcr(DCR_SDRAM0_CFGDATA);
153 ear = mfdcr(DCR_SDRAM0_CFGDATA);
232 esr = mfdcr(DCR_SDRAM0_CFGDATA);
270 esr = mfdcr(DCR_SDRAM0_CFGDATA);
mal.c 87 while (mfdcr(DCR_MAL0_CFG) & MAL0_CFG_SR) {
145 while ((tcei = mfdcr(DCR_MAL0_TXEOBISR))) {
161 while ((rcei = mfdcr(DCR_MAL0_RXEOBISR))) {
179 while ((txde = mfdcr(DCR_MAL0_TXDEIR))) {
197 while ((rxde = mfdcr(DCR_MAL0_RXDEIR))) {
217 esr = mfdcr(DCR_MAL0_ESR);
exb.c 89 ebc0_bNcr = mfdcr(DCR_EBC0_CFGDATA);
opb.c 346 pllmr = mfdcr(DCR_CPC0_PLLMR);
dwcsata.c 281 mfdcr(DCR_PLB4A0_ACR), mfdcr(DCR_PLB4A1_ACR),
  /src/sys/arch/powerpc/ibm4xx/pci/
pciex.c 296 mfdcr((base) + PEGPL_CFG) & ~PEGPL_CFG_PLE); \

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