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    Searched refs:mg_pll_div0 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 206 u32 mg_pll_div0; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 2864 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
2885 pll_state->mg_pll_div0 =
3170 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
3238 hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
3239 hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK |
3384 I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3440 val |= hw_state->mg_pll_div0;
3654 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x,
    [all...]
intel_ddi.c 1464 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1466 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1477 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1479 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1480 m2_frac = pll_state->mg_pll_div0 &
intel_display.c 13691 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_debugfs.c 2770 seq_printf(m, " mg_pll_div0: 0x%08x\n",
2771 pll->state.hw_state.mg_pll_div0);

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