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    Searched refs:mg_pll_div1 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 207 u32 mg_pll_div1; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 2869 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
2890 pll_state->mg_pll_div1 =
3171 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
3244 hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
3245 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
3385 I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3446 val |= hw_state->mg_pll_div1;
3663 hw_state->mg_pll_div1,
    [all...]
intel_ddi.c 1476 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
intel_display.c 13692 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_debugfs.c 2772 seq_printf(m, " mg_pll_div1: 0x%08x\n",
2773 pll->state.hw_state.mg_pll_div1);

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