| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.c | 430 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
440 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
442 else if (min_cdclk > 266667)
444 else if (min_cdclk > 0)
665 static int bdw_calc_cdclk(int min_cdclk)
667 if (min_cdclk > 540000)
669 else if (min_cdclk > 450000)
671 else if (min_cdclk > 337500)
793 static int skl_calc_cdclk(int min_cdclk, int vco)
796 if (min_cdclk > 540000
1933 int min_cdclk = 0; local in function:intel_planes_min_cdclk
1945 int min_cdclk; local in function:intel_crtc_compute_min_cdclk
2038 int min_cdclk, i; local in function:intel_compute_min_cdclk
2122 int min_cdclk, cdclk; local in function:vlv_modeset_calc_cdclk
2149 int min_cdclk, cdclk; local in function:bdw_modeset_calc_cdclk
2216 int min_cdclk, cdclk, vco; local in function:skl_modeset_calc_cdclk
2252 int min_cdclk, min_voltage_level, cdclk, vco; local in function:bxt_modeset_calc_cdclk
2327 int min_cdclk; local in function:fixed_modeset_calc_cdclk
[all...] |
| intel_atomic_plane.c | 172 if (!plane_state->uapi.visible || !plane->min_cdclk)
177 crtc_state->min_cdclk[plane->id] =
178 plane->min_cdclk(crtc_state, plane_state);
190 if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) {
191 DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
193 crtc_state->min_cdclk[plane->id],
243 new_crtc_state->min_cdclk[plane->id] = 0;
|
| intel_atomic.c | 511 memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
|
| intel_display_types.h | 498 int min_cdclk[I915_MAX_PIPES]; member in struct:intel_atomic_state
514 * min_cdclk[]
993 int min_cdclk[I915_MAX_PLANES]; member in struct:intel_crtc_state
1140 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, member in struct:intel_plane
|
| intel_sprite.c | 2981 plane->min_cdclk = skl_plane_min_cdclk;
3085 plane->min_cdclk = vlv_plane_min_cdclk;
3105 plane->min_cdclk = hsw_plane_min_cdclk;
3107 plane->min_cdclk = ivb_sprite_min_cdclk;
3120 plane->min_cdclk = g4x_sprite_min_cdclk;
|
| intel_display.c | 3512 crtc_state->min_cdclk[plane->id] = 0;
7557 dev_priv->min_cdclk[pipe] = 0;
12173 crtc_state->min_cdclk[plane->id] = 0;
15621 memcpy(dev_priv->min_cdclk, state->min_cdclk,
15622 sizeof(state->min_cdclk));
16217 plane->min_cdclk = vlv_plane_min_cdclk;
16219 plane->min_cdclk = hsw_plane_min_cdclk;
16221 plane->min_cdclk = ivb_plane_min_cdclk;
16223 plane->min_cdclk = i9xx_plane_min_cdclk
18204 int min_cdclk = 0; local in function:intel_modeset_readout_hw_state
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 1111 * For reading active_pipes, min_cdclk, min_voltage_level holding
1116 int min_cdclk[I915_MAX_PIPES]; member in struct:drm_i915_private
|
