| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 142 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
151 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
378 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
387 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
413 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
414 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",
415 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 212 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
221 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
1234 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1244 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1277 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1286 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1313 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 169 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs.min_chunk_size);
|
| display_mode_structs.h | 496 unsigned int min_chunk_size; member in struct:_vcs_dpi_display_data_rq_regs_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 222 rq_regs->min_chunk_size = 0;
224 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 219 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
222 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
|
| amdgpu_dcn10_hubp.c | 560 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
569 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
1042 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1052 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
|
| amdgpu_dcn10_hw_sequencer.c | 207 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
210 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
1792 "min_chunk_size: %d \n"
1802 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 180 rq_regs->min_chunk_size = 0;
182 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
|
| amdgpu_display_rq_dlg_calc_20v2.c | 180 rq_regs->min_chunk_size = 0;
182 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 157 rq_regs->min_chunk_size = 0;
159 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
|
