| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 463 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
478 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
479 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
480 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 210 "DML_RQ_DLG_CALC: min_dst_y_next_start = 0x%0x\n",
211 dlg_regs.min_dst_y_next_start);
|
| display_mode_structs.h | 422 unsigned int min_dst_y_next_start; member in struct:_vcs_dpi_display_dlg_regs_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 1162 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
1164 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
1174 "DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x",
1176 disp_dlg_regs->min_dst_y_next_start);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 97 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
1072 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1365 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1380 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1381 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
1382 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 937 disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2));
938 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
952 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
954 disp_dlg_regs->min_dst_y_next_start);
|
| amdgpu_display_rq_dlg_calc_20v2.c | 937 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
939 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
953 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
955 disp_dlg_regs->min_dst_y_next_start);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 983 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
984 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
1003 "DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",
1005 disp_dlg_regs->min_dst_y_next_start);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 265 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
|
| amdgpu_dcn10_hubp.c | 592 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
880 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
|
| amdgpu_dcn10_hw_sequencer.c | 232 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
1728 "min_dst_y_next_start: %d, \n"
1744 pipe_ctx->dlg_regs.min_dst_y_next_start,
|
