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    Searched refs:min_ref_div (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_display.c 983 ref_div_min = pll->min_ref_div;
1114 uint32_t min_ref_div = pll->min_ref_div; local in function:radeon_compute_pll_legacy
1131 DRM_DEBUG_KMS("PLL freq %"PRIu64" %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1146 min_ref_div = max_ref_div = pll->reference_div;
1148 while (min_ref_div < max_ref_div-1) {
1149 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1154 min_ref_div = mid;
1187 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
radeon_clocks.c 309 dcpll->min_ref_div = 2;
315 p1pll->min_ref_div = 2;
321 p2pll->min_ref_div = 2;
330 spll->min_ref_div = 2;
339 mpll->min_ref_div = 2;
radeon_mode.h 185 uint32_t min_ref_div; member in struct:radeon_pll
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_pll.c 151 ref_div_min = pll->min_ref_div;
amdgpu_atomfirmware.c 393 spll->min_ref_div = 2;
416 mpll->min_ref_div = 2;
amdgpu_mode.h 210 uint32_t min_ref_div; member in struct:amdgpu_pll
amdgpu_atombios.c 613 ppll->min_ref_div = 2;
643 spll->min_ref_div = 2;
675 mpll->min_ref_div = 2;

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