| /src/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
| fixed31_32.h | 194 * | min_value, when arg <= min_value
195 * result = | arg, when min_value < arg < max_value
200 struct fixed31_32 min_value,
203 if (dc_fixpt_le(arg, min_value))
204 return min_value;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| vega20_ppt.h | 163 int32_t min_value; member in struct:vega20_od8_single_setting
|
| amdgpu_navi10_ppt.c | 780 uint32_t min_value, max_value; local in function:navi10_print_clk_levels
901 &min_value, NULL);
905 min_value, max_value);
910 &min_value, &max_value);
912 min_value, max_value);
917 &min_value, &max_value);
919 min_value, max_value);
921 &min_value, &max_value);
923 min_value, max_value);
925 &min_value, &max_value)
[all...] |
| amdgpu_vega20_ppt.c | 1142 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1169 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1172 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1175 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1178 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1181 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1670 od8_settings->od8_settings_array[i].min_value =
1677 od8_settings->od8_settings_array[i].min_value = 0;
2437 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
[all...] |
| amdgpu_smu.c | 368 uint32_t *min_value, uint32_t *max_value)
373 if (!min_value && !max_value)
376 if (min_value) {
378 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega20_hwmgr.c | 1348 od8_settings->od8_settings_array[i].min_value =
1355 od8_settings->od8_settings_array[i].min_value =
1393 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1418 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
2956 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2960 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2999 if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
3003 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3046 if (input_clk < od8_settings[od8_id].min_value ||
3050 od8_settings[od8_id].min_value,
[all...] |
| vega20_hwmgr.h | 427 int32_t min_value; member in struct:vega20_od8_single_setting
|
| /src/usr.bin/xlint/lint1/ |
| tree.c | 1160 int64_t min_value, int64_t max_value, bool *overflow)
1168 *overflow = l == min_value;
1177 return neg ? min_value : max_value;
1186 if (l == min_value && r == -1) {
1197 if (l == min_value && r == -1) {
1207 if (r < 0 && l < min_value - r) {
1209 return min_value;
1213 if (r > 0 && l < min_value + r) {
1215 return min_value;
1286 int64_t min_value = -max_value - 1 local in function:fold_constant_integer
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_sprite.c | 629 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
1052 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
1470 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
1781 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
|
| /src/usr.sbin/envstat/ |
| envstat.c | 73 int32_t min_value; member in struct:envsys_sensor
732 sensor->min_value = prop_number_signed_value(obj1);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 716 uint32_t *min_value, uint32_t *max_value);
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| i915_drm.h | 1507 __u32 min_value; member in struct:drm_intel_sprite_colorkey
|
