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    Searched refs:mis (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/dev/acpi/
plgpio_acpi.c 211 uint32_t mis; local
214 mis = PLGPIO_READ(sc, PL061_GPIOMIS_REG);
215 PLGPIO_WRITE(sc, PL061_GPIOIC_REG, mis);
217 while ((bit = __builtin_ffs(mis)) != 0) {
224 mis &= ~__BIT(pin);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_resource.c 795 if (pool->base.mis[i] != NULL) {
796 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
797 pool->base.mis[i] = NULL;
1031 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1032 if (pool->base.mis[i] == NULL) {
1228 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1229 if (pool->base.mis[i] == NULL) {
1421 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1422 if (pool->base.mis[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c 804 if (pool->base.mis[i] != NULL) {
805 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
806 pool->base.mis[i] = NULL;
1114 pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1246 pool->mis[pool->pipe_count] = &dce110_miv->base;
1423 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1424 if (pool->base.mis[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_resource.c 747 if (pool->base.mis[i] != NULL) {
748 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
749 pool->base.mis[i] = NULL;
1065 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1066 if (pool->base.mis[i] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 609 if (pool->base.mis[i] != NULL) {
610 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
611 pool->base.mis[i] = NULL;
1157 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1159 if (pool->base.mis[j] == NULL) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 161 struct mem_input *mis[MAX_PIPES]; member in struct:resource_pool
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 765 if (pool->base.mis[i] != NULL) {
766 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
767 pool->base.mis[i] = NULL;
1307 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1308 if (pool->base.mis[i] == NULL) {
  /src/sys/arch/m68k/m68k/
busaddrerr.s 96 btst #27,%d0 | check for mis-aligned access
134 btst #11,%d0 | check for mis-aligned
  /src/sys/arch/atari/atari/
locore.s 125 btst #27,%d0 | check for mis-aligned access
149 btst #11,%d0 | check for mis-aligned
  /src/sys/arch/amiga/amiga/
locore.s 139 btst #27,%d0 | check for mis-aligned access
162 btst #11,%d0 | check for mis-aligned
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 1647 pipe_ctx->plane_res.mi = pool->mis[i];
1918 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1737 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1812 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 525 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];

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