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    Searched refs:misc1 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 261 uint32_t misc1 = 0; local
315 misc1 = REG_READ(DP_MSA_MISC);
317 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
318 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
319 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
322 misc1 = misc1 | 0x40;
324 misc1 = misc1 & ~0x40;
378 misc1 = misc1 & ~0x80; /* bit7 = 0*
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 290 uint32_t misc1 = 0; local
351 misc1 = REG_READ(DP_MSA_MISC);
409 misc1 = misc1 & ~0x80; /* bit7 = 0*/
414 misc1 = misc1 & ~0x80; /* bit7 = 0*/
420 misc1 = misc1 & ~0x80; /* bit7 = 0*/
431 misc1 = misc1 & ~0x80; /* bit7 = 0*
    [all...]

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