1 /* $NetBSD: mmhub_9_4_1_default.h,v 1.2 2021/12/18 23:45:16 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _mmhub_9_4_1_DEFAULT_HEADER 24 #define _mmhub_9_4_1_DEFAULT_HEADER 25 26 27 // addressBlock: mmhub_dagb_dagbdec0 28 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 29 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 30 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 31 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 32 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 33 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 34 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 35 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 36 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 37 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 38 #define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 39 #define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 40 #define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 41 #define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 42 #define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 43 #define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 44 #define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 45 #define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003045 46 #define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 47 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 48 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 49 #define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 50 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 51 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 52 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 53 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 54 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 55 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 56 #define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 57 #define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 58 #define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 59 #define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 60 #define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 61 #define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 62 #define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 63 #define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 64 #define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x69a0e408 65 #define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 66 #define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 67 #define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 68 #define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 69 #define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 70 #define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 71 #define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 72 #define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 73 #define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 74 #define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 75 #define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 76 #define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 77 #define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 78 #define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 79 #define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 80 #define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 81 #define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 82 #define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 83 #define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 84 #define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 85 #define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 86 #define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 87 #define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 88 #define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 89 #define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003045 90 #define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 91 #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 92 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 93 #define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 94 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 95 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 96 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 97 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 98 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 99 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 100 #define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 101 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 102 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 103 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 104 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 105 #define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 106 #define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 107 #define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 108 #define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 109 #define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 110 #define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 111 #define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 112 #define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 113 #define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x69a0e408 114 #define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 115 #define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070 116 #define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 117 #define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 118 #define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 119 #define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 120 #define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 121 #define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 122 #define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 123 #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 124 #define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 125 #define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 126 #define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa 127 #define mmDAGB0_CNTL_MISC2_DEFAULT 0x003c0000 128 #define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff 129 #define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 130 #define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x1fffffff 131 #define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff 132 #define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 133 #define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 134 #define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 135 #define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 136 #define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 137 #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 138 #define mmDAGB0_RESERVE0_DEFAULT 0xffffffff 139 #define mmDAGB0_RESERVE1_DEFAULT 0xffffffff 140 #define mmDAGB0_RESERVE2_DEFAULT 0xffffffff 141 #define mmDAGB0_RESERVE3_DEFAULT 0xffffffff 142 #define mmDAGB0_RESERVE4_DEFAULT 0xffffffff 143 #define mmDAGB0_RESERVE5_DEFAULT 0xffffffff 144 #define mmDAGB0_RESERVE6_DEFAULT 0xffffffff 145 #define mmDAGB0_RESERVE7_DEFAULT 0xffffffff 146 #define mmDAGB0_RESERVE8_DEFAULT 0xffffffff 147 #define mmDAGB0_RESERVE9_DEFAULT 0xffffffff 148 #define mmDAGB0_RESERVE10_DEFAULT 0xffffffff 149 #define mmDAGB0_RESERVE11_DEFAULT 0xffffffff 150 #define mmDAGB0_RESERVE12_DEFAULT 0xffffffff 151 #define mmDAGB0_RESERVE13_DEFAULT 0xffffffff 152 153 154 // addressBlock: mmhub_dagb_dagbdec1 155 #define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9 156 #define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9 157 #define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9 158 #define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9 159 #define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9 160 #define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9 161 #define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9 162 #define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9 163 #define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9 164 #define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9 165 #define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9 166 #define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9 167 #define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9 168 #define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9 169 #define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9 170 #define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9 171 #define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8 172 #define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x00003045 173 #define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039 174 #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 175 #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 176 #define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 177 #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 178 #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 179 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 180 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 181 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 182 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 183 #define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082 184 #define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082 185 #define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082 186 #define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082 187 #define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082 188 #define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082 189 #define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082 190 #define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082 191 #define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x69a0e408 192 #define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 193 #define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000 194 #define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000 195 #define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 196 #define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000 197 #define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000 198 #define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000 199 #define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9 200 #define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9 201 #define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9 202 #define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9 203 #define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9 204 #define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9 205 #define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9 206 #define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9 207 #define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9 208 #define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9 209 #define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9 210 #define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9 211 #define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9 212 #define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9 213 #define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9 214 #define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9 215 #define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8 216 #define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x00003045 217 #define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039 218 #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 219 #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 220 #define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 221 #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 222 #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 223 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 224 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 225 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 226 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 227 #define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001 228 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 229 #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 230 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 231 #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 232 #define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082 233 #define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082 234 #define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082 235 #define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082 236 #define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082 237 #define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082 238 #define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082 239 #define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082 240 #define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x69a0e408 241 #define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 242 #define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x60606070 243 #define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88 244 #define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000 245 #define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000 246 #define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 247 #define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000 248 #define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000 249 #define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000 250 #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 251 #define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 252 #define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000 253 #define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa 254 #define mmDAGB1_CNTL_MISC2_DEFAULT 0x003c0000 255 #define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff 256 #define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000 257 #define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x1fffffff 258 #define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff 259 #define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000 260 #define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000 261 #define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 262 #define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 263 #define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 264 #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 265 #define mmDAGB1_RESERVE0_DEFAULT 0xffffffff 266 #define mmDAGB1_RESERVE1_DEFAULT 0xffffffff 267 #define mmDAGB1_RESERVE2_DEFAULT 0xffffffff 268 #define mmDAGB1_RESERVE3_DEFAULT 0xffffffff 269 #define mmDAGB1_RESERVE4_DEFAULT 0xffffffff 270 #define mmDAGB1_RESERVE5_DEFAULT 0xffffffff 271 #define mmDAGB1_RESERVE6_DEFAULT 0xffffffff 272 #define mmDAGB1_RESERVE7_DEFAULT 0xffffffff 273 #define mmDAGB1_RESERVE8_DEFAULT 0xffffffff 274 #define mmDAGB1_RESERVE9_DEFAULT 0xffffffff 275 #define mmDAGB1_RESERVE10_DEFAULT 0xffffffff 276 #define mmDAGB1_RESERVE11_DEFAULT 0xffffffff 277 #define mmDAGB1_RESERVE12_DEFAULT 0xffffffff 278 #define mmDAGB1_RESERVE13_DEFAULT 0xffffffff 279 280 281 // addressBlock: mmhub_dagb_dagbdec2 282 #define mmDAGB2_RDCLI0_DEFAULT 0xfe5fe0f9 283 #define mmDAGB2_RDCLI1_DEFAULT 0xfe5fe0f9 284 #define mmDAGB2_RDCLI2_DEFAULT 0xfe5fe0f9 285 #define mmDAGB2_RDCLI3_DEFAULT 0xfe5fe0f9 286 #define mmDAGB2_RDCLI4_DEFAULT 0xfe5fe0f9 287 #define mmDAGB2_RDCLI5_DEFAULT 0xfe5fe0f9 288 #define mmDAGB2_RDCLI6_DEFAULT 0xfe5fe0f9 289 #define mmDAGB2_RDCLI7_DEFAULT 0xfe5fe0f9 290 #define mmDAGB2_RDCLI8_DEFAULT 0xfe5fe0f9 291 #define mmDAGB2_RDCLI9_DEFAULT 0xfe5fe0f9 292 #define mmDAGB2_RDCLI10_DEFAULT 0xfe5fe0f9 293 #define mmDAGB2_RDCLI11_DEFAULT 0xfe5fe0f9 294 #define mmDAGB2_RDCLI12_DEFAULT 0xfe5fe0f9 295 #define mmDAGB2_RDCLI13_DEFAULT 0xfe5fe0f9 296 #define mmDAGB2_RDCLI14_DEFAULT 0xfe5fe0f9 297 #define mmDAGB2_RDCLI15_DEFAULT 0xfe5fe0f9 298 #define mmDAGB2_RD_CNTL_DEFAULT 0x03527df8 299 #define mmDAGB2_RD_GMI_CNTL_DEFAULT 0x00003045 300 #define mmDAGB2_RD_ADDR_DAGB_DEFAULT 0x00000039 301 #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 302 #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 303 #define mmDAGB2_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 304 #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 305 #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 306 #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 307 #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 308 #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 309 #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 310 #define mmDAGB2_RD_VC0_CNTL_DEFAULT 0xff2ff082 311 #define mmDAGB2_RD_VC1_CNTL_DEFAULT 0xff2ff082 312 #define mmDAGB2_RD_VC2_CNTL_DEFAULT 0xff2ff082 313 #define mmDAGB2_RD_VC3_CNTL_DEFAULT 0xff2ff082 314 #define mmDAGB2_RD_VC4_CNTL_DEFAULT 0xff2ff082 315 #define mmDAGB2_RD_VC5_CNTL_DEFAULT 0xff2ff082 316 #define mmDAGB2_RD_VC6_CNTL_DEFAULT 0xff2ff082 317 #define mmDAGB2_RD_VC7_CNTL_DEFAULT 0xff2ff082 318 #define mmDAGB2_RD_CNTL_MISC_DEFAULT 0x69a0e408 319 #define mmDAGB2_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 320 #define mmDAGB2_RDCLI_ASK_PENDING_DEFAULT 0x00000000 321 #define mmDAGB2_RDCLI_GO_PENDING_DEFAULT 0x00000000 322 #define mmDAGB2_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 323 #define mmDAGB2_RDCLI_TLB_PENDING_DEFAULT 0x00000000 324 #define mmDAGB2_RDCLI_OARB_PENDING_DEFAULT 0x00000000 325 #define mmDAGB2_RDCLI_OSD_PENDING_DEFAULT 0x00000000 326 #define mmDAGB2_WRCLI0_DEFAULT 0xfe5fe0f9 327 #define mmDAGB2_WRCLI1_DEFAULT 0xfe5fe0f9 328 #define mmDAGB2_WRCLI2_DEFAULT 0xfe5fe0f9 329 #define mmDAGB2_WRCLI3_DEFAULT 0xfe5fe0f9 330 #define mmDAGB2_WRCLI4_DEFAULT 0xfe5fe0f9 331 #define mmDAGB2_WRCLI5_DEFAULT 0xfe5fe0f9 332 #define mmDAGB2_WRCLI6_DEFAULT 0xfe5fe0f9 333 #define mmDAGB2_WRCLI7_DEFAULT 0xfe5fe0f9 334 #define mmDAGB2_WRCLI8_DEFAULT 0xfe5fe0f9 335 #define mmDAGB2_WRCLI9_DEFAULT 0xfe5fe0f9 336 #define mmDAGB2_WRCLI10_DEFAULT 0xfe5fe0f9 337 #define mmDAGB2_WRCLI11_DEFAULT 0xfe5fe0f9 338 #define mmDAGB2_WRCLI12_DEFAULT 0xfe5fe0f9 339 #define mmDAGB2_WRCLI13_DEFAULT 0xfe5fe0f9 340 #define mmDAGB2_WRCLI14_DEFAULT 0xfe5fe0f9 341 #define mmDAGB2_WRCLI15_DEFAULT 0xfe5fe0f9 342 #define mmDAGB2_WR_CNTL_DEFAULT 0x03527df8 343 #define mmDAGB2_WR_GMI_CNTL_DEFAULT 0x00003045 344 #define mmDAGB2_WR_ADDR_DAGB_DEFAULT 0x00000039 345 #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 346 #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 347 #define mmDAGB2_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 348 #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 349 #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 350 #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 351 #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 352 #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 353 #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 354 #define mmDAGB2_WR_DATA_DAGB_DEFAULT 0x00000001 355 #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 356 #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 357 #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 358 #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 359 #define mmDAGB2_WR_VC0_CNTL_DEFAULT 0xff2ff082 360 #define mmDAGB2_WR_VC1_CNTL_DEFAULT 0xff2ff082 361 #define mmDAGB2_WR_VC2_CNTL_DEFAULT 0xff2ff082 362 #define mmDAGB2_WR_VC3_CNTL_DEFAULT 0xff2ff082 363 #define mmDAGB2_WR_VC4_CNTL_DEFAULT 0xff2ff082 364 #define mmDAGB2_WR_VC5_CNTL_DEFAULT 0xff2ff082 365 #define mmDAGB2_WR_VC6_CNTL_DEFAULT 0xff2ff082 366 #define mmDAGB2_WR_VC7_CNTL_DEFAULT 0xff2ff082 367 #define mmDAGB2_WR_CNTL_MISC_DEFAULT 0x69a0e408 368 #define mmDAGB2_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 369 #define mmDAGB2_WR_DATA_CREDIT_DEFAULT 0x60606070 370 #define mmDAGB2_WR_MISC_CREDIT_DEFAULT 0x0078dc88 371 #define mmDAGB2_WRCLI_ASK_PENDING_DEFAULT 0x00000000 372 #define mmDAGB2_WRCLI_GO_PENDING_DEFAULT 0x00000000 373 #define mmDAGB2_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 374 #define mmDAGB2_WRCLI_TLB_PENDING_DEFAULT 0x00000000 375 #define mmDAGB2_WRCLI_OARB_PENDING_DEFAULT 0x00000000 376 #define mmDAGB2_WRCLI_OSD_PENDING_DEFAULT 0x00000000 377 #define mmDAGB2_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 378 #define mmDAGB2_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 379 #define mmDAGB2_DAGB_DLY_DEFAULT 0x00000000 380 #define mmDAGB2_CNTL_MISC_DEFAULT 0xcf7c1ffa 381 #define mmDAGB2_CNTL_MISC2_DEFAULT 0x003c0000 382 #define mmDAGB2_FIFO_EMPTY_DEFAULT 0x00ffffff 383 #define mmDAGB2_FIFO_FULL_DEFAULT 0x00000000 384 #define mmDAGB2_WR_CREDITS_FULL_DEFAULT 0x1fffffff 385 #define mmDAGB2_RD_CREDITS_FULL_DEFAULT 0x0003ffff 386 #define mmDAGB2_PERFCOUNTER_LO_DEFAULT 0x00000000 387 #define mmDAGB2_PERFCOUNTER_HI_DEFAULT 0x00000000 388 #define mmDAGB2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 389 #define mmDAGB2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 390 #define mmDAGB2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 391 #define mmDAGB2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 392 #define mmDAGB2_RESERVE0_DEFAULT 0xffffffff 393 #define mmDAGB2_RESERVE1_DEFAULT 0xffffffff 394 #define mmDAGB2_RESERVE2_DEFAULT 0xffffffff 395 #define mmDAGB2_RESERVE3_DEFAULT 0xffffffff 396 #define mmDAGB2_RESERVE4_DEFAULT 0xffffffff 397 #define mmDAGB2_RESERVE5_DEFAULT 0xffffffff 398 #define mmDAGB2_RESERVE6_DEFAULT 0xffffffff 399 #define mmDAGB2_RESERVE7_DEFAULT 0xffffffff 400 #define mmDAGB2_RESERVE8_DEFAULT 0xffffffff 401 #define mmDAGB2_RESERVE9_DEFAULT 0xffffffff 402 #define mmDAGB2_RESERVE10_DEFAULT 0xffffffff 403 #define mmDAGB2_RESERVE11_DEFAULT 0xffffffff 404 #define mmDAGB2_RESERVE12_DEFAULT 0xffffffff 405 #define mmDAGB2_RESERVE13_DEFAULT 0xffffffff 406 407 408 // addressBlock: mmhub_dagb_dagbdec3 409 #define mmDAGB3_RDCLI0_DEFAULT 0xfe5fe0f9 410 #define mmDAGB3_RDCLI1_DEFAULT 0xfe5fe0f9 411 #define mmDAGB3_RDCLI2_DEFAULT 0xfe5fe0f9 412 #define mmDAGB3_RDCLI3_DEFAULT 0xfe5fe0f9 413 #define mmDAGB3_RDCLI4_DEFAULT 0xfe5fe0f9 414 #define mmDAGB3_RDCLI5_DEFAULT 0xfe5fe0f9 415 #define mmDAGB3_RDCLI6_DEFAULT 0xfe5fe0f9 416 #define mmDAGB3_RDCLI7_DEFAULT 0xfe5fe0f9 417 #define mmDAGB3_RDCLI8_DEFAULT 0xfe5fe0f9 418 #define mmDAGB3_RDCLI9_DEFAULT 0xfe5fe0f9 419 #define mmDAGB3_RDCLI10_DEFAULT 0xfe5fe0f9 420 #define mmDAGB3_RDCLI11_DEFAULT 0xfe5fe0f9 421 #define mmDAGB3_RDCLI12_DEFAULT 0xfe5fe0f9 422 #define mmDAGB3_RDCLI13_DEFAULT 0xfe5fe0f9 423 #define mmDAGB3_RDCLI14_DEFAULT 0xfe5fe0f9 424 #define mmDAGB3_RDCLI15_DEFAULT 0xfe5fe0f9 425 #define mmDAGB3_RD_CNTL_DEFAULT 0x03527df8 426 #define mmDAGB3_RD_GMI_CNTL_DEFAULT 0x00003045 427 #define mmDAGB3_RD_ADDR_DAGB_DEFAULT 0x00000039 428 #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 429 #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 430 #define mmDAGB3_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 431 #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 432 #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 433 #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 434 #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 435 #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 436 #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 437 #define mmDAGB3_RD_VC0_CNTL_DEFAULT 0xff2ff082 438 #define mmDAGB3_RD_VC1_CNTL_DEFAULT 0xff2ff082 439 #define mmDAGB3_RD_VC2_CNTL_DEFAULT 0xff2ff082 440 #define mmDAGB3_RD_VC3_CNTL_DEFAULT 0xff2ff082 441 #define mmDAGB3_RD_VC4_CNTL_DEFAULT 0xff2ff082 442 #define mmDAGB3_RD_VC5_CNTL_DEFAULT 0xff2ff082 443 #define mmDAGB3_RD_VC6_CNTL_DEFAULT 0xff2ff082 444 #define mmDAGB3_RD_VC7_CNTL_DEFAULT 0xff2ff082 445 #define mmDAGB3_RD_CNTL_MISC_DEFAULT 0x69a0e408 446 #define mmDAGB3_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 447 #define mmDAGB3_RDCLI_ASK_PENDING_DEFAULT 0x00000000 448 #define mmDAGB3_RDCLI_GO_PENDING_DEFAULT 0x00000000 449 #define mmDAGB3_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 450 #define mmDAGB3_RDCLI_TLB_PENDING_DEFAULT 0x00000000 451 #define mmDAGB3_RDCLI_OARB_PENDING_DEFAULT 0x00000000 452 #define mmDAGB3_RDCLI_OSD_PENDING_DEFAULT 0x00000000 453 #define mmDAGB3_WRCLI0_DEFAULT 0xfe5fe0f9 454 #define mmDAGB3_WRCLI1_DEFAULT 0xfe5fe0f9 455 #define mmDAGB3_WRCLI2_DEFAULT 0xfe5fe0f9 456 #define mmDAGB3_WRCLI3_DEFAULT 0xfe5fe0f9 457 #define mmDAGB3_WRCLI4_DEFAULT 0xfe5fe0f9 458 #define mmDAGB3_WRCLI5_DEFAULT 0xfe5fe0f9 459 #define mmDAGB3_WRCLI6_DEFAULT 0xfe5fe0f9 460 #define mmDAGB3_WRCLI7_DEFAULT 0xfe5fe0f9 461 #define mmDAGB3_WRCLI8_DEFAULT 0xfe5fe0f9 462 #define mmDAGB3_WRCLI9_DEFAULT 0xfe5fe0f9 463 #define mmDAGB3_WRCLI10_DEFAULT 0xfe5fe0f9 464 #define mmDAGB3_WRCLI11_DEFAULT 0xfe5fe0f9 465 #define mmDAGB3_WRCLI12_DEFAULT 0xfe5fe0f9 466 #define mmDAGB3_WRCLI13_DEFAULT 0xfe5fe0f9 467 #define mmDAGB3_WRCLI14_DEFAULT 0xfe5fe0f9 468 #define mmDAGB3_WRCLI15_DEFAULT 0xfe5fe0f9 469 #define mmDAGB3_WR_CNTL_DEFAULT 0x03527df8 470 #define mmDAGB3_WR_GMI_CNTL_DEFAULT 0x00003045 471 #define mmDAGB3_WR_ADDR_DAGB_DEFAULT 0x00000039 472 #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 473 #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 474 #define mmDAGB3_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 475 #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 476 #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 477 #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 478 #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 479 #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 480 #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 481 #define mmDAGB3_WR_DATA_DAGB_DEFAULT 0x00000001 482 #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 483 #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 484 #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 485 #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 486 #define mmDAGB3_WR_VC0_CNTL_DEFAULT 0xff2ff082 487 #define mmDAGB3_WR_VC1_CNTL_DEFAULT 0xff2ff082 488 #define mmDAGB3_WR_VC2_CNTL_DEFAULT 0xff2ff082 489 #define mmDAGB3_WR_VC3_CNTL_DEFAULT 0xff2ff082 490 #define mmDAGB3_WR_VC4_CNTL_DEFAULT 0xff2ff082 491 #define mmDAGB3_WR_VC5_CNTL_DEFAULT 0xff2ff082 492 #define mmDAGB3_WR_VC6_CNTL_DEFAULT 0xff2ff082 493 #define mmDAGB3_WR_VC7_CNTL_DEFAULT 0xff2ff082 494 #define mmDAGB3_WR_CNTL_MISC_DEFAULT 0x69a0e408 495 #define mmDAGB3_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 496 #define mmDAGB3_WR_DATA_CREDIT_DEFAULT 0x60606070 497 #define mmDAGB3_WR_MISC_CREDIT_DEFAULT 0x0078dc88 498 #define mmDAGB3_WRCLI_ASK_PENDING_DEFAULT 0x00000000 499 #define mmDAGB3_WRCLI_GO_PENDING_DEFAULT 0x00000000 500 #define mmDAGB3_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 501 #define mmDAGB3_WRCLI_TLB_PENDING_DEFAULT 0x00000000 502 #define mmDAGB3_WRCLI_OARB_PENDING_DEFAULT 0x00000000 503 #define mmDAGB3_WRCLI_OSD_PENDING_DEFAULT 0x00000000 504 #define mmDAGB3_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 505 #define mmDAGB3_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 506 #define mmDAGB3_DAGB_DLY_DEFAULT 0x00000000 507 #define mmDAGB3_CNTL_MISC_DEFAULT 0xcf7c1ffa 508 #define mmDAGB3_CNTL_MISC2_DEFAULT 0x003c0000 509 #define mmDAGB3_FIFO_EMPTY_DEFAULT 0x00ffffff 510 #define mmDAGB3_FIFO_FULL_DEFAULT 0x00000000 511 #define mmDAGB3_WR_CREDITS_FULL_DEFAULT 0x1fffffff 512 #define mmDAGB3_RD_CREDITS_FULL_DEFAULT 0x0003ffff 513 #define mmDAGB3_PERFCOUNTER_LO_DEFAULT 0x00000000 514 #define mmDAGB3_PERFCOUNTER_HI_DEFAULT 0x00000000 515 #define mmDAGB3_PERFCOUNTER0_CFG_DEFAULT 0x00000000 516 #define mmDAGB3_PERFCOUNTER1_CFG_DEFAULT 0x00000000 517 #define mmDAGB3_PERFCOUNTER2_CFG_DEFAULT 0x00000000 518 #define mmDAGB3_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 519 #define mmDAGB3_RESERVE0_DEFAULT 0xffffffff 520 #define mmDAGB3_RESERVE1_DEFAULT 0xffffffff 521 #define mmDAGB3_RESERVE2_DEFAULT 0xffffffff 522 #define mmDAGB3_RESERVE3_DEFAULT 0xffffffff 523 #define mmDAGB3_RESERVE4_DEFAULT 0xffffffff 524 #define mmDAGB3_RESERVE5_DEFAULT 0xffffffff 525 #define mmDAGB3_RESERVE6_DEFAULT 0xffffffff 526 #define mmDAGB3_RESERVE7_DEFAULT 0xffffffff 527 #define mmDAGB3_RESERVE8_DEFAULT 0xffffffff 528 #define mmDAGB3_RESERVE9_DEFAULT 0xffffffff 529 #define mmDAGB3_RESERVE10_DEFAULT 0xffffffff 530 #define mmDAGB3_RESERVE11_DEFAULT 0xffffffff 531 #define mmDAGB3_RESERVE12_DEFAULT 0xffffffff 532 #define mmDAGB3_RESERVE13_DEFAULT 0xffffffff 533 534 535 // addressBlock: mmhub_dagb_dagbdec4 536 #define mmDAGB4_RDCLI0_DEFAULT 0xfe5fe0f9 537 #define mmDAGB4_RDCLI1_DEFAULT 0xfe5fe0f9 538 #define mmDAGB4_RDCLI2_DEFAULT 0xfe5fe0f9 539 #define mmDAGB4_RDCLI3_DEFAULT 0xfe5fe0f9 540 #define mmDAGB4_RDCLI4_DEFAULT 0xfe5fe0f9 541 #define mmDAGB4_RDCLI5_DEFAULT 0xfe5fe0f9 542 #define mmDAGB4_RDCLI6_DEFAULT 0xfe5fe0f9 543 #define mmDAGB4_RDCLI7_DEFAULT 0xfe5fe0f9 544 #define mmDAGB4_RDCLI8_DEFAULT 0xfe5fe0f9 545 #define mmDAGB4_RDCLI9_DEFAULT 0xfe5fe0f9 546 #define mmDAGB4_RDCLI10_DEFAULT 0xfe5fe0f9 547 #define mmDAGB4_RDCLI11_DEFAULT 0xfe5fe0f9 548 #define mmDAGB4_RDCLI12_DEFAULT 0xfe5fe0f9 549 #define mmDAGB4_RDCLI13_DEFAULT 0xfe5fe0f9 550 #define mmDAGB4_RDCLI14_DEFAULT 0xfe5fe0f9 551 #define mmDAGB4_RDCLI15_DEFAULT 0xfe5fe0f9 552 #define mmDAGB4_RD_CNTL_DEFAULT 0x03527df8 553 #define mmDAGB4_RD_GMI_CNTL_DEFAULT 0x00003045 554 #define mmDAGB4_RD_ADDR_DAGB_DEFAULT 0x00000039 555 #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 556 #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 557 #define mmDAGB4_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 558 #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 559 #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 560 #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 561 #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 562 #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 563 #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 564 #define mmDAGB4_RD_VC0_CNTL_DEFAULT 0xff2ff082 565 #define mmDAGB4_RD_VC1_CNTL_DEFAULT 0xff2ff082 566 #define mmDAGB4_RD_VC2_CNTL_DEFAULT 0xff2ff082 567 #define mmDAGB4_RD_VC3_CNTL_DEFAULT 0xff2ff082 568 #define mmDAGB4_RD_VC4_CNTL_DEFAULT 0xff2ff082 569 #define mmDAGB4_RD_VC5_CNTL_DEFAULT 0xff2ff082 570 #define mmDAGB4_RD_VC6_CNTL_DEFAULT 0xff2ff082 571 #define mmDAGB4_RD_VC7_CNTL_DEFAULT 0xff2ff082 572 #define mmDAGB4_RD_CNTL_MISC_DEFAULT 0x69a0e408 573 #define mmDAGB4_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 574 #define mmDAGB4_RDCLI_ASK_PENDING_DEFAULT 0x00000000 575 #define mmDAGB4_RDCLI_GO_PENDING_DEFAULT 0x00000000 576 #define mmDAGB4_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 577 #define mmDAGB4_RDCLI_TLB_PENDING_DEFAULT 0x00000000 578 #define mmDAGB4_RDCLI_OARB_PENDING_DEFAULT 0x00000000 579 #define mmDAGB4_RDCLI_OSD_PENDING_DEFAULT 0x00000000 580 #define mmDAGB4_WRCLI0_DEFAULT 0xfe5fe0f9 581 #define mmDAGB4_WRCLI1_DEFAULT 0xfe5fe0f9 582 #define mmDAGB4_WRCLI2_DEFAULT 0xfe5fe0f9 583 #define mmDAGB4_WRCLI3_DEFAULT 0xfe5fe0f9 584 #define mmDAGB4_WRCLI4_DEFAULT 0xfe5fe0f9 585 #define mmDAGB4_WRCLI5_DEFAULT 0xfe5fe0f9 586 #define mmDAGB4_WRCLI6_DEFAULT 0xfe5fe0f9 587 #define mmDAGB4_WRCLI7_DEFAULT 0xfe5fe0f9 588 #define mmDAGB4_WRCLI8_DEFAULT 0xfe5fe0f9 589 #define mmDAGB4_WRCLI9_DEFAULT 0xfe5fe0f9 590 #define mmDAGB4_WRCLI10_DEFAULT 0xfe5fe0f9 591 #define mmDAGB4_WRCLI11_DEFAULT 0xfe5fe0f9 592 #define mmDAGB4_WRCLI12_DEFAULT 0xfe5fe0f9 593 #define mmDAGB4_WRCLI13_DEFAULT 0xfe5fe0f9 594 #define mmDAGB4_WRCLI14_DEFAULT 0xfe5fe0f9 595 #define mmDAGB4_WRCLI15_DEFAULT 0xfe5fe0f9 596 #define mmDAGB4_WR_CNTL_DEFAULT 0x03527df8 597 #define mmDAGB4_WR_GMI_CNTL_DEFAULT 0x00003045 598 #define mmDAGB4_WR_ADDR_DAGB_DEFAULT 0x00000039 599 #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 600 #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 601 #define mmDAGB4_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 602 #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 603 #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 604 #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 605 #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 606 #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 607 #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 608 #define mmDAGB4_WR_DATA_DAGB_DEFAULT 0x00000001 609 #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 610 #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 611 #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 612 #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 613 #define mmDAGB4_WR_VC0_CNTL_DEFAULT 0xff2ff082 614 #define mmDAGB4_WR_VC1_CNTL_DEFAULT 0xff2ff082 615 #define mmDAGB4_WR_VC2_CNTL_DEFAULT 0xff2ff082 616 #define mmDAGB4_WR_VC3_CNTL_DEFAULT 0xff2ff082 617 #define mmDAGB4_WR_VC4_CNTL_DEFAULT 0xff2ff082 618 #define mmDAGB4_WR_VC5_CNTL_DEFAULT 0xff2ff082 619 #define mmDAGB4_WR_VC6_CNTL_DEFAULT 0xff2ff082 620 #define mmDAGB4_WR_VC7_CNTL_DEFAULT 0xff2ff082 621 #define mmDAGB4_WR_CNTL_MISC_DEFAULT 0x69a0e408 622 #define mmDAGB4_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 623 #define mmDAGB4_WR_DATA_CREDIT_DEFAULT 0x60606070 624 #define mmDAGB4_WR_MISC_CREDIT_DEFAULT 0x0078dc88 625 #define mmDAGB4_WRCLI_ASK_PENDING_DEFAULT 0x00000000 626 #define mmDAGB4_WRCLI_GO_PENDING_DEFAULT 0x00000000 627 #define mmDAGB4_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 628 #define mmDAGB4_WRCLI_TLB_PENDING_DEFAULT 0x00000000 629 #define mmDAGB4_WRCLI_OARB_PENDING_DEFAULT 0x00000000 630 #define mmDAGB4_WRCLI_OSD_PENDING_DEFAULT 0x00000000 631 #define mmDAGB4_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 632 #define mmDAGB4_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 633 #define mmDAGB4_DAGB_DLY_DEFAULT 0x00000000 634 #define mmDAGB4_CNTL_MISC_DEFAULT 0xcf7c1ffa 635 #define mmDAGB4_CNTL_MISC2_DEFAULT 0x003c0000 636 #define mmDAGB4_FIFO_EMPTY_DEFAULT 0x00ffffff 637 #define mmDAGB4_FIFO_FULL_DEFAULT 0x00000000 638 #define mmDAGB4_WR_CREDITS_FULL_DEFAULT 0x1fffffff 639 #define mmDAGB4_RD_CREDITS_FULL_DEFAULT 0x0003ffff 640 #define mmDAGB4_PERFCOUNTER_LO_DEFAULT 0x00000000 641 #define mmDAGB4_PERFCOUNTER_HI_DEFAULT 0x00000000 642 #define mmDAGB4_PERFCOUNTER0_CFG_DEFAULT 0x00000000 643 #define mmDAGB4_PERFCOUNTER1_CFG_DEFAULT 0x00000000 644 #define mmDAGB4_PERFCOUNTER2_CFG_DEFAULT 0x00000000 645 #define mmDAGB4_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 646 #define mmDAGB4_RESERVE0_DEFAULT 0xffffffff 647 #define mmDAGB4_RESERVE1_DEFAULT 0xffffffff 648 #define mmDAGB4_RESERVE2_DEFAULT 0xffffffff 649 #define mmDAGB4_RESERVE3_DEFAULT 0xffffffff 650 #define mmDAGB4_RESERVE4_DEFAULT 0xffffffff 651 #define mmDAGB4_RESERVE5_DEFAULT 0xffffffff 652 #define mmDAGB4_RESERVE6_DEFAULT 0xffffffff 653 #define mmDAGB4_RESERVE7_DEFAULT 0xffffffff 654 #define mmDAGB4_RESERVE8_DEFAULT 0xffffffff 655 #define mmDAGB4_RESERVE9_DEFAULT 0xffffffff 656 #define mmDAGB4_RESERVE10_DEFAULT 0xffffffff 657 #define mmDAGB4_RESERVE11_DEFAULT 0xffffffff 658 #define mmDAGB4_RESERVE12_DEFAULT 0xffffffff 659 #define mmDAGB4_RESERVE13_DEFAULT 0xffffffff 660 661 662 // addressBlock: mmhub_ea_mmeadec0 663 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 664 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 665 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 666 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 667 #define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 668 #define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 669 #define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924 670 #define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924 671 #define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 672 #define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 673 #define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 674 #define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 675 #define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 676 #define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 677 #define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 678 #define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 679 #define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 680 #define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 681 #define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 682 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 683 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 684 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 685 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 686 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 687 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 688 #define mmMMEA0_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 689 #define mmMMEA0_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 690 #define mmMMEA0_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 691 #define mmMMEA0_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 692 #define mmMMEA0_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 693 #define mmMMEA0_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 694 #define mmMMEA0_GMI_RD_LAZY_DEFAULT 0x78000924 695 #define mmMMEA0_GMI_WR_LAZY_DEFAULT 0x78000924 696 #define mmMMEA0_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 697 #define mmMMEA0_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 698 #define mmMMEA0_GMI_PAGE_BURST_DEFAULT 0x20002000 699 #define mmMMEA0_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 700 #define mmMMEA0_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 701 #define mmMMEA0_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 702 #define mmMMEA0_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 703 #define mmMMEA0_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 704 #define mmMMEA0_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 705 #define mmMMEA0_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 706 #define mmMMEA0_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 707 #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 708 #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 709 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 710 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 711 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 712 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 713 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 714 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 715 #define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 716 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 717 #define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 718 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 719 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 720 #define mmMMEA0_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 721 #define mmMMEA0_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 722 #define mmMMEA0_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 723 #define mmMMEA0_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 724 #define mmMMEA0_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 725 #define mmMMEA0_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 726 #define mmMMEA0_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 727 #define mmMMEA0_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 728 #define mmMMEA0_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 729 #define mmMMEA0_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 730 #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 731 #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 732 #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 733 #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 734 #define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 735 #define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 736 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 737 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 738 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 739 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 740 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 741 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 742 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 743 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 744 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 745 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 746 #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 747 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 748 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 749 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 750 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 751 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 752 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 753 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 754 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 755 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 756 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 757 #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 758 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 759 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 760 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 761 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 762 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 763 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 764 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 765 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 766 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 767 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 768 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 769 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 770 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 771 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 772 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 773 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 774 #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 775 #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 776 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 777 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 778 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 779 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 780 #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 781 #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 782 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 783 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 784 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 785 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 786 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 787 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 788 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 789 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 790 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 791 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 792 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 793 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 794 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 795 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 796 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 797 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 798 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 799 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 800 #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 801 #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 802 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 803 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 804 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 805 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 806 #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 807 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 808 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 809 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 810 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 811 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 812 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 813 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 814 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 815 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 816 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 817 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 818 #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 819 #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 820 #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 821 #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 822 #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 823 #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 824 #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 825 #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 826 #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 827 #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 828 #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 829 #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 830 #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 831 #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 832 #define mmMMEA0_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 833 #define mmMMEA0_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 834 #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 835 #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 836 #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 837 #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 838 #define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 839 #define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 840 #define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 841 #define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 842 #define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 843 #define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 844 #define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 845 #define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 846 #define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 847 #define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 848 #define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 849 #define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 850 #define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 851 #define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 852 #define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 853 #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 854 #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 855 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 856 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 857 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 858 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 859 #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 860 #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 861 #define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40 862 #define mmMMEA0_SDP_ARB_GMI_DEFAULT 0x00101e40 863 #define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff 864 #define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 865 #define mmMMEA0_SDP_GMI_PRIORITY_DEFAULT 0x00000000 866 #define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 867 #define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf 868 #define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 869 #define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 870 #define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 871 #define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 872 #define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 873 #define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 874 #define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000001f 875 #define mmMMEA0_MISC_DEFAULT 0x0c00a070 876 #define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 877 #define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 878 #define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 879 #define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 880 #define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 881 #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 882 #define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 883 #define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 884 #define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 885 #define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 886 #define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 887 #define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 888 #define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 889 #define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 890 #define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 891 #define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 892 #define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300 893 #define mmMMEA0_MISC2_DEFAULT 0x00000000 894 #define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000 895 #define mmMMEA0_EDC_CNT3_DEFAULT 0x00000000 896 897 898 // addressBlock: mmhub_ea_mmeadec1 899 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 900 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 901 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 902 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 903 #define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 904 #define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 905 #define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x78000924 906 #define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x78000924 907 #define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 908 #define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 909 #define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 910 #define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 911 #define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 912 #define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 913 #define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 914 #define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 915 #define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 916 #define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 917 #define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 918 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 919 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 920 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 921 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 922 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 923 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 924 #define mmMMEA1_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 925 #define mmMMEA1_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 926 #define mmMMEA1_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 927 #define mmMMEA1_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 928 #define mmMMEA1_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 929 #define mmMMEA1_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 930 #define mmMMEA1_GMI_RD_LAZY_DEFAULT 0x78000924 931 #define mmMMEA1_GMI_WR_LAZY_DEFAULT 0x78000924 932 #define mmMMEA1_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 933 #define mmMMEA1_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 934 #define mmMMEA1_GMI_PAGE_BURST_DEFAULT 0x20002000 935 #define mmMMEA1_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 936 #define mmMMEA1_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 937 #define mmMMEA1_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 938 #define mmMMEA1_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 939 #define mmMMEA1_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 940 #define mmMMEA1_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 941 #define mmMMEA1_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 942 #define mmMMEA1_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 943 #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 944 #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 945 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 946 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 947 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 948 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 949 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 950 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 951 #define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 952 #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 953 #define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 954 #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 955 #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 956 #define mmMMEA1_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 957 #define mmMMEA1_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 958 #define mmMMEA1_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 959 #define mmMMEA1_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 960 #define mmMMEA1_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 961 #define mmMMEA1_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 962 #define mmMMEA1_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 963 #define mmMMEA1_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 964 #define mmMMEA1_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 965 #define mmMMEA1_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 966 #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 967 #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 968 #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 969 #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 970 #define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 971 #define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 972 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 973 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 974 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 975 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 976 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 977 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 978 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 979 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 980 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 981 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 982 #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 983 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 984 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 985 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 986 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 987 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 988 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 989 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 990 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 991 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 992 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 993 #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 994 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 995 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 996 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 997 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 998 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 999 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1000 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1001 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1002 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1003 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1004 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1005 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1006 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 1007 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 1008 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 1009 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 1010 #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 1011 #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 1012 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 1013 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 1014 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1015 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1016 #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 1017 #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 1018 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 1019 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 1020 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 1021 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 1022 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 1023 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 1024 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1025 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1026 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1027 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1028 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1029 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1030 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1031 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1032 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 1033 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 1034 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 1035 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 1036 #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 1037 #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 1038 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 1039 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 1040 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1041 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1042 #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 1043 #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 1044 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 1045 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 1046 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 1047 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 1048 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 1049 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 1050 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1051 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1052 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1053 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1054 #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1055 #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1056 #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1057 #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1058 #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 1059 #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 1060 #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 1061 #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 1062 #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 1063 #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 1064 #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 1065 #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 1066 #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1067 #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1068 #define mmMMEA1_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 1069 #define mmMMEA1_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 1070 #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 1071 #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 1072 #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 1073 #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 1074 #define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1075 #define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1076 #define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1077 #define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1078 #define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 1079 #define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 1080 #define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 1081 #define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 1082 #define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 1083 #define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 1084 #define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 1085 #define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 1086 #define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 1087 #define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 1088 #define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 1089 #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1090 #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1091 #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1092 #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1093 #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1094 #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1095 #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1096 #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1097 #define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00101e40 1098 #define mmMMEA1_SDP_ARB_GMI_DEFAULT 0x00101e40 1099 #define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff 1100 #define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 1101 #define mmMMEA1_SDP_GMI_PRIORITY_DEFAULT 0x00000000 1102 #define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 1103 #define mmMMEA1_SDP_CREDITS_DEFAULT 0x000101bf 1104 #define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 1105 #define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 1106 #define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 1107 #define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 1108 #define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 1109 #define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 1110 #define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000001f 1111 #define mmMMEA1_MISC_DEFAULT 0x0c00a070 1112 #define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 1113 #define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 1114 #define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 1115 #define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 1116 #define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 1117 #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 1118 #define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 1119 #define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 1120 #define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 1121 #define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 1122 #define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 1123 #define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 1124 #define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 1125 #define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 1126 #define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 1127 #define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 1128 #define mmMMEA1_ERR_STATUS_DEFAULT 0x00000300 1129 #define mmMMEA1_MISC2_DEFAULT 0x00000000 1130 #define mmMMEA1_ADDRDEC_SELECT_DEFAULT 0x00000000 1131 #define mmMMEA1_EDC_CNT3_DEFAULT 0x00000000 1132 1133 1134 // addressBlock: mmhub_ea_mmeadec2 1135 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 1136 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 1137 #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 1138 #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 1139 #define mmMMEA2_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 1140 #define mmMMEA2_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 1141 #define mmMMEA2_DRAM_RD_LAZY_DEFAULT 0x78000924 1142 #define mmMMEA2_DRAM_WR_LAZY_DEFAULT 0x78000924 1143 #define mmMMEA2_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 1144 #define mmMMEA2_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 1145 #define mmMMEA2_DRAM_PAGE_BURST_DEFAULT 0x20002000 1146 #define mmMMEA2_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 1147 #define mmMMEA2_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 1148 #define mmMMEA2_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 1149 #define mmMMEA2_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 1150 #define mmMMEA2_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 1151 #define mmMMEA2_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 1152 #define mmMMEA2_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 1153 #define mmMMEA2_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 1154 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1155 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1156 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1157 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1158 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1159 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1160 #define mmMMEA2_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 1161 #define mmMMEA2_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 1162 #define mmMMEA2_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 1163 #define mmMMEA2_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 1164 #define mmMMEA2_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 1165 #define mmMMEA2_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 1166 #define mmMMEA2_GMI_RD_LAZY_DEFAULT 0x78000924 1167 #define mmMMEA2_GMI_WR_LAZY_DEFAULT 0x78000924 1168 #define mmMMEA2_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 1169 #define mmMMEA2_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 1170 #define mmMMEA2_GMI_PAGE_BURST_DEFAULT 0x20002000 1171 #define mmMMEA2_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 1172 #define mmMMEA2_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 1173 #define mmMMEA2_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 1174 #define mmMMEA2_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 1175 #define mmMMEA2_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 1176 #define mmMMEA2_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 1177 #define mmMMEA2_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 1178 #define mmMMEA2_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 1179 #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1180 #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1181 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1182 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1183 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1184 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1185 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1186 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1187 #define mmMMEA2_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 1188 #define mmMMEA2_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 1189 #define mmMMEA2_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 1190 #define mmMMEA2_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 1191 #define mmMMEA2_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 1192 #define mmMMEA2_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 1193 #define mmMMEA2_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 1194 #define mmMMEA2_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 1195 #define mmMMEA2_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 1196 #define mmMMEA2_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 1197 #define mmMMEA2_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 1198 #define mmMMEA2_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 1199 #define mmMMEA2_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 1200 #define mmMMEA2_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 1201 #define mmMMEA2_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 1202 #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 1203 #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 1204 #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 1205 #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 1206 #define mmMMEA2_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 1207 #define mmMMEA2_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 1208 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 1209 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 1210 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 1211 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 1212 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 1213 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 1214 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 1215 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 1216 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 1217 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 1218 #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 1219 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 1220 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 1221 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 1222 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 1223 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 1224 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 1225 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 1226 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 1227 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 1228 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 1229 #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 1230 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 1231 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 1232 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 1233 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 1234 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1235 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1236 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1237 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1238 #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1239 #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1240 #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1241 #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1242 #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 1243 #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 1244 #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 1245 #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 1246 #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 1247 #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 1248 #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 1249 #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 1250 #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1251 #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1252 #define mmMMEA2_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 1253 #define mmMMEA2_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 1254 #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 1255 #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 1256 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 1257 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 1258 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 1259 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 1260 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1261 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1262 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1263 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1264 #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1265 #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1266 #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1267 #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1268 #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 1269 #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 1270 #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 1271 #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 1272 #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 1273 #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 1274 #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 1275 #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 1276 #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1277 #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1278 #define mmMMEA2_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 1279 #define mmMMEA2_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 1280 #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 1281 #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 1282 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 1283 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 1284 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 1285 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 1286 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1287 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1288 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1289 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1290 #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1291 #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1292 #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1293 #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1294 #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 1295 #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 1296 #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 1297 #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 1298 #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 1299 #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 1300 #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 1301 #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 1302 #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1303 #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1304 #define mmMMEA2_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 1305 #define mmMMEA2_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 1306 #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 1307 #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 1308 #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 1309 #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 1310 #define mmMMEA2_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1311 #define mmMMEA2_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1312 #define mmMMEA2_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1313 #define mmMMEA2_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1314 #define mmMMEA2_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 1315 #define mmMMEA2_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 1316 #define mmMMEA2_IO_GROUP_BURST_DEFAULT 0x1f031f03 1317 #define mmMMEA2_IO_RD_PRI_AGE_DEFAULT 0x00db6249 1318 #define mmMMEA2_IO_WR_PRI_AGE_DEFAULT 0x00db6249 1319 #define mmMMEA2_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 1320 #define mmMMEA2_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 1321 #define mmMMEA2_IO_RD_PRI_FIXED_DEFAULT 0x00000924 1322 #define mmMMEA2_IO_WR_PRI_FIXED_DEFAULT 0x00000924 1323 #define mmMMEA2_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 1324 #define mmMMEA2_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 1325 #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1326 #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1327 #define mmMMEA2_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1328 #define mmMMEA2_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1329 #define mmMMEA2_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1330 #define mmMMEA2_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1331 #define mmMMEA2_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1332 #define mmMMEA2_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1333 #define mmMMEA2_SDP_ARB_DRAM_DEFAULT 0x00101e40 1334 #define mmMMEA2_SDP_ARB_GMI_DEFAULT 0x00101e40 1335 #define mmMMEA2_SDP_ARB_FINAL_DEFAULT 0x00007fff 1336 #define mmMMEA2_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 1337 #define mmMMEA2_SDP_GMI_PRIORITY_DEFAULT 0x00000000 1338 #define mmMMEA2_SDP_IO_PRIORITY_DEFAULT 0x00000000 1339 #define mmMMEA2_SDP_CREDITS_DEFAULT 0x000101bf 1340 #define mmMMEA2_SDP_TAG_RESERVE0_DEFAULT 0x00000000 1341 #define mmMMEA2_SDP_TAG_RESERVE1_DEFAULT 0x00000000 1342 #define mmMMEA2_SDP_VCC_RESERVE0_DEFAULT 0x00000000 1343 #define mmMMEA2_SDP_VCC_RESERVE1_DEFAULT 0x00000000 1344 #define mmMMEA2_SDP_VCD_RESERVE0_DEFAULT 0x00000000 1345 #define mmMMEA2_SDP_VCD_RESERVE1_DEFAULT 0x00000000 1346 #define mmMMEA2_SDP_REQ_CNTL_DEFAULT 0x0000001f 1347 #define mmMMEA2_MISC_DEFAULT 0x0c00a070 1348 #define mmMMEA2_LATENCY_SAMPLING_DEFAULT 0x00000000 1349 #define mmMMEA2_PERFCOUNTER_LO_DEFAULT 0x00000000 1350 #define mmMMEA2_PERFCOUNTER_HI_DEFAULT 0x00000000 1351 #define mmMMEA2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 1352 #define mmMMEA2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 1353 #define mmMMEA2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 1354 #define mmMMEA2_EDC_CNT_DEFAULT 0x00000000 1355 #define mmMMEA2_EDC_CNT2_DEFAULT 0x00000000 1356 #define mmMMEA2_DSM_CNTL_DEFAULT 0x00000000 1357 #define mmMMEA2_DSM_CNTLA_DEFAULT 0x00000000 1358 #define mmMMEA2_DSM_CNTLB_DEFAULT 0x00000000 1359 #define mmMMEA2_DSM_CNTL2_DEFAULT 0x00000000 1360 #define mmMMEA2_DSM_CNTL2A_DEFAULT 0x00000000 1361 #define mmMMEA2_DSM_CNTL2B_DEFAULT 0x00000000 1362 #define mmMMEA2_CGTT_CLK_CTRL_DEFAULT 0x00000100 1363 #define mmMMEA2_EDC_MODE_DEFAULT 0x00000000 1364 #define mmMMEA2_ERR_STATUS_DEFAULT 0x00000300 1365 #define mmMMEA2_MISC2_DEFAULT 0x00000000 1366 #define mmMMEA2_ADDRDEC_SELECT_DEFAULT 0x00000000 1367 #define mmMMEA2_EDC_CNT3_DEFAULT 0x00000000 1368 1369 1370 // addressBlock: mmhub_ea_mmeadec3 1371 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 1372 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 1373 #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 1374 #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 1375 #define mmMMEA3_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 1376 #define mmMMEA3_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 1377 #define mmMMEA3_DRAM_RD_LAZY_DEFAULT 0x78000924 1378 #define mmMMEA3_DRAM_WR_LAZY_DEFAULT 0x78000924 1379 #define mmMMEA3_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 1380 #define mmMMEA3_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 1381 #define mmMMEA3_DRAM_PAGE_BURST_DEFAULT 0x20002000 1382 #define mmMMEA3_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 1383 #define mmMMEA3_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 1384 #define mmMMEA3_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 1385 #define mmMMEA3_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 1386 #define mmMMEA3_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 1387 #define mmMMEA3_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 1388 #define mmMMEA3_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 1389 #define mmMMEA3_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 1390 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1391 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1392 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1393 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1394 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1395 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1396 #define mmMMEA3_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 1397 #define mmMMEA3_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 1398 #define mmMMEA3_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 1399 #define mmMMEA3_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 1400 #define mmMMEA3_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 1401 #define mmMMEA3_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 1402 #define mmMMEA3_GMI_RD_LAZY_DEFAULT 0x78000924 1403 #define mmMMEA3_GMI_WR_LAZY_DEFAULT 0x78000924 1404 #define mmMMEA3_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 1405 #define mmMMEA3_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 1406 #define mmMMEA3_GMI_PAGE_BURST_DEFAULT 0x20002000 1407 #define mmMMEA3_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 1408 #define mmMMEA3_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 1409 #define mmMMEA3_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 1410 #define mmMMEA3_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 1411 #define mmMMEA3_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 1412 #define mmMMEA3_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 1413 #define mmMMEA3_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 1414 #define mmMMEA3_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 1415 #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1416 #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1417 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1418 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1419 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1420 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1421 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1422 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1423 #define mmMMEA3_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 1424 #define mmMMEA3_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 1425 #define mmMMEA3_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 1426 #define mmMMEA3_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 1427 #define mmMMEA3_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 1428 #define mmMMEA3_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 1429 #define mmMMEA3_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 1430 #define mmMMEA3_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 1431 #define mmMMEA3_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 1432 #define mmMMEA3_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 1433 #define mmMMEA3_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 1434 #define mmMMEA3_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 1435 #define mmMMEA3_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 1436 #define mmMMEA3_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 1437 #define mmMMEA3_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 1438 #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 1439 #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 1440 #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 1441 #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 1442 #define mmMMEA3_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 1443 #define mmMMEA3_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 1444 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 1445 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 1446 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 1447 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 1448 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 1449 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 1450 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 1451 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 1452 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 1453 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 1454 #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 1455 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 1456 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 1457 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 1458 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 1459 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 1460 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 1461 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 1462 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 1463 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 1464 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 1465 #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 1466 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 1467 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 1468 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 1469 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 1470 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1471 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1472 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1473 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1474 #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1475 #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1476 #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1477 #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1478 #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 1479 #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 1480 #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 1481 #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 1482 #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 1483 #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 1484 #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 1485 #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 1486 #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1487 #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1488 #define mmMMEA3_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 1489 #define mmMMEA3_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 1490 #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 1491 #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 1492 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 1493 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 1494 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 1495 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 1496 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1497 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1498 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1499 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1500 #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1501 #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1502 #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1503 #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1504 #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 1505 #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 1506 #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 1507 #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 1508 #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 1509 #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 1510 #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 1511 #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 1512 #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1513 #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1514 #define mmMMEA3_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 1515 #define mmMMEA3_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 1516 #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 1517 #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 1518 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 1519 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 1520 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 1521 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 1522 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1523 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1524 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1525 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1526 #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1527 #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1528 #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1529 #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1530 #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 1531 #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 1532 #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 1533 #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 1534 #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 1535 #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 1536 #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 1537 #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 1538 #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1539 #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1540 #define mmMMEA3_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 1541 #define mmMMEA3_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 1542 #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 1543 #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 1544 #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 1545 #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 1546 #define mmMMEA3_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1547 #define mmMMEA3_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1548 #define mmMMEA3_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1549 #define mmMMEA3_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1550 #define mmMMEA3_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 1551 #define mmMMEA3_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 1552 #define mmMMEA3_IO_GROUP_BURST_DEFAULT 0x1f031f03 1553 #define mmMMEA3_IO_RD_PRI_AGE_DEFAULT 0x00db6249 1554 #define mmMMEA3_IO_WR_PRI_AGE_DEFAULT 0x00db6249 1555 #define mmMMEA3_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 1556 #define mmMMEA3_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 1557 #define mmMMEA3_IO_RD_PRI_FIXED_DEFAULT 0x00000924 1558 #define mmMMEA3_IO_WR_PRI_FIXED_DEFAULT 0x00000924 1559 #define mmMMEA3_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 1560 #define mmMMEA3_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 1561 #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1562 #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1563 #define mmMMEA3_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1564 #define mmMMEA3_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1565 #define mmMMEA3_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1566 #define mmMMEA3_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1567 #define mmMMEA3_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1568 #define mmMMEA3_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1569 #define mmMMEA3_SDP_ARB_DRAM_DEFAULT 0x00101e40 1570 #define mmMMEA3_SDP_ARB_GMI_DEFAULT 0x00101e40 1571 #define mmMMEA3_SDP_ARB_FINAL_DEFAULT 0x00007fff 1572 #define mmMMEA3_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 1573 #define mmMMEA3_SDP_GMI_PRIORITY_DEFAULT 0x00000000 1574 #define mmMMEA3_SDP_IO_PRIORITY_DEFAULT 0x00000000 1575 #define mmMMEA3_SDP_CREDITS_DEFAULT 0x000101bf 1576 #define mmMMEA3_SDP_TAG_RESERVE0_DEFAULT 0x00000000 1577 #define mmMMEA3_SDP_TAG_RESERVE1_DEFAULT 0x00000000 1578 #define mmMMEA3_SDP_VCC_RESERVE0_DEFAULT 0x00000000 1579 #define mmMMEA3_SDP_VCC_RESERVE1_DEFAULT 0x00000000 1580 #define mmMMEA3_SDP_VCD_RESERVE0_DEFAULT 0x00000000 1581 #define mmMMEA3_SDP_VCD_RESERVE1_DEFAULT 0x00000000 1582 #define mmMMEA3_SDP_REQ_CNTL_DEFAULT 0x0000001f 1583 #define mmMMEA3_MISC_DEFAULT 0x0c00a070 1584 #define mmMMEA3_LATENCY_SAMPLING_DEFAULT 0x00000000 1585 #define mmMMEA3_PERFCOUNTER_LO_DEFAULT 0x00000000 1586 #define mmMMEA3_PERFCOUNTER_HI_DEFAULT 0x00000000 1587 #define mmMMEA3_PERFCOUNTER0_CFG_DEFAULT 0x00000000 1588 #define mmMMEA3_PERFCOUNTER1_CFG_DEFAULT 0x00000000 1589 #define mmMMEA3_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 1590 #define mmMMEA3_EDC_CNT_DEFAULT 0x00000000 1591 #define mmMMEA3_EDC_CNT2_DEFAULT 0x00000000 1592 #define mmMMEA3_DSM_CNTL_DEFAULT 0x00000000 1593 #define mmMMEA3_DSM_CNTLA_DEFAULT 0x00000000 1594 #define mmMMEA3_DSM_CNTLB_DEFAULT 0x00000000 1595 #define mmMMEA3_DSM_CNTL2_DEFAULT 0x00000000 1596 #define mmMMEA3_DSM_CNTL2A_DEFAULT 0x00000000 1597 #define mmMMEA3_DSM_CNTL2B_DEFAULT 0x00000000 1598 #define mmMMEA3_CGTT_CLK_CTRL_DEFAULT 0x00000100 1599 #define mmMMEA3_EDC_MODE_DEFAULT 0x00000000 1600 #define mmMMEA3_ERR_STATUS_DEFAULT 0x00000300 1601 #define mmMMEA3_MISC2_DEFAULT 0x00000000 1602 #define mmMMEA3_ADDRDEC_SELECT_DEFAULT 0x00000000 1603 #define mmMMEA3_EDC_CNT3_DEFAULT 0x00000000 1604 1605 1606 // addressBlock: mmhub_ea_mmeadec4 1607 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 1608 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 1609 #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 1610 #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 1611 #define mmMMEA4_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 1612 #define mmMMEA4_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 1613 #define mmMMEA4_DRAM_RD_LAZY_DEFAULT 0x78000924 1614 #define mmMMEA4_DRAM_WR_LAZY_DEFAULT 0x78000924 1615 #define mmMMEA4_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 1616 #define mmMMEA4_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 1617 #define mmMMEA4_DRAM_PAGE_BURST_DEFAULT 0x20002000 1618 #define mmMMEA4_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 1619 #define mmMMEA4_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 1620 #define mmMMEA4_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 1621 #define mmMMEA4_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 1622 #define mmMMEA4_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 1623 #define mmMMEA4_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 1624 #define mmMMEA4_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 1625 #define mmMMEA4_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 1626 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1627 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1628 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1629 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1630 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1631 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1632 #define mmMMEA4_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 1633 #define mmMMEA4_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 1634 #define mmMMEA4_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 1635 #define mmMMEA4_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 1636 #define mmMMEA4_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 1637 #define mmMMEA4_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 1638 #define mmMMEA4_GMI_RD_LAZY_DEFAULT 0x78000924 1639 #define mmMMEA4_GMI_WR_LAZY_DEFAULT 0x78000924 1640 #define mmMMEA4_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 1641 #define mmMMEA4_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 1642 #define mmMMEA4_GMI_PAGE_BURST_DEFAULT 0x20002000 1643 #define mmMMEA4_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 1644 #define mmMMEA4_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 1645 #define mmMMEA4_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 1646 #define mmMMEA4_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 1647 #define mmMMEA4_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 1648 #define mmMMEA4_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 1649 #define mmMMEA4_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 1650 #define mmMMEA4_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 1651 #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1652 #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1653 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1654 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1655 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1656 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1657 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1658 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1659 #define mmMMEA4_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 1660 #define mmMMEA4_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 1661 #define mmMMEA4_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 1662 #define mmMMEA4_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 1663 #define mmMMEA4_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 1664 #define mmMMEA4_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 1665 #define mmMMEA4_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 1666 #define mmMMEA4_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 1667 #define mmMMEA4_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 1668 #define mmMMEA4_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 1669 #define mmMMEA4_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 1670 #define mmMMEA4_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 1671 #define mmMMEA4_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 1672 #define mmMMEA4_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 1673 #define mmMMEA4_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 1674 #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 1675 #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 1676 #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 1677 #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 1678 #define mmMMEA4_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 1679 #define mmMMEA4_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 1680 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 1681 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 1682 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 1683 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 1684 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 1685 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 1686 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 1687 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 1688 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 1689 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 1690 #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 1691 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 1692 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 1693 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 1694 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 1695 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 1696 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 1697 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 1698 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 1699 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 1700 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 1701 #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 1702 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 1703 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 1704 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 1705 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 1706 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1707 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1708 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1709 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1710 #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1711 #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1712 #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1713 #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1714 #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 1715 #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 1716 #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 1717 #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 1718 #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 1719 #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 1720 #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 1721 #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 1722 #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1723 #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1724 #define mmMMEA4_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 1725 #define mmMMEA4_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 1726 #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 1727 #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 1728 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 1729 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 1730 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 1731 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 1732 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1733 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1734 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1735 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1736 #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1737 #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1738 #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1739 #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1740 #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 1741 #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 1742 #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 1743 #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 1744 #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 1745 #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 1746 #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 1747 #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 1748 #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1749 #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1750 #define mmMMEA4_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 1751 #define mmMMEA4_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 1752 #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 1753 #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 1754 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 1755 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 1756 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 1757 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 1758 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 1759 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 1760 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 1761 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 1762 #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 1763 #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 1764 #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 1765 #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 1766 #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 1767 #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 1768 #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 1769 #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 1770 #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 1771 #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 1772 #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 1773 #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 1774 #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 1775 #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 1776 #define mmMMEA4_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 1777 #define mmMMEA4_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 1778 #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 1779 #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 1780 #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 1781 #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 1782 #define mmMMEA4_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1783 #define mmMMEA4_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1784 #define mmMMEA4_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 1785 #define mmMMEA4_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 1786 #define mmMMEA4_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 1787 #define mmMMEA4_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 1788 #define mmMMEA4_IO_GROUP_BURST_DEFAULT 0x1f031f03 1789 #define mmMMEA4_IO_RD_PRI_AGE_DEFAULT 0x00db6249 1790 #define mmMMEA4_IO_WR_PRI_AGE_DEFAULT 0x00db6249 1791 #define mmMMEA4_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 1792 #define mmMMEA4_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 1793 #define mmMMEA4_IO_RD_PRI_FIXED_DEFAULT 0x00000924 1794 #define mmMMEA4_IO_WR_PRI_FIXED_DEFAULT 0x00000924 1795 #define mmMMEA4_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 1796 #define mmMMEA4_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 1797 #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1798 #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 1799 #define mmMMEA4_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1800 #define mmMMEA4_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1801 #define mmMMEA4_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1802 #define mmMMEA4_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 1803 #define mmMMEA4_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 1804 #define mmMMEA4_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 1805 #define mmMMEA4_SDP_ARB_DRAM_DEFAULT 0x00101e40 1806 #define mmMMEA4_SDP_ARB_GMI_DEFAULT 0x00101e40 1807 #define mmMMEA4_SDP_ARB_FINAL_DEFAULT 0x00007fff 1808 #define mmMMEA4_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 1809 #define mmMMEA4_SDP_GMI_PRIORITY_DEFAULT 0x00000000 1810 #define mmMMEA4_SDP_IO_PRIORITY_DEFAULT 0x00000000 1811 #define mmMMEA4_SDP_CREDITS_DEFAULT 0x000101bf 1812 #define mmMMEA4_SDP_TAG_RESERVE0_DEFAULT 0x00000000 1813 #define mmMMEA4_SDP_TAG_RESERVE1_DEFAULT 0x00000000 1814 #define mmMMEA4_SDP_VCC_RESERVE0_DEFAULT 0x00000000 1815 #define mmMMEA4_SDP_VCC_RESERVE1_DEFAULT 0x00000000 1816 #define mmMMEA4_SDP_VCD_RESERVE0_DEFAULT 0x00000000 1817 #define mmMMEA4_SDP_VCD_RESERVE1_DEFAULT 0x00000000 1818 #define mmMMEA4_SDP_REQ_CNTL_DEFAULT 0x0000001f 1819 #define mmMMEA4_MISC_DEFAULT 0x0c00a070 1820 #define mmMMEA4_LATENCY_SAMPLING_DEFAULT 0x00000000 1821 #define mmMMEA4_PERFCOUNTER_LO_DEFAULT 0x00000000 1822 #define mmMMEA4_PERFCOUNTER_HI_DEFAULT 0x00000000 1823 #define mmMMEA4_PERFCOUNTER0_CFG_DEFAULT 0x00000000 1824 #define mmMMEA4_PERFCOUNTER1_CFG_DEFAULT 0x00000000 1825 #define mmMMEA4_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 1826 #define mmMMEA4_EDC_CNT_DEFAULT 0x00000000 1827 #define mmMMEA4_EDC_CNT2_DEFAULT 0x00000000 1828 #define mmMMEA4_DSM_CNTL_DEFAULT 0x00000000 1829 #define mmMMEA4_DSM_CNTLA_DEFAULT 0x00000000 1830 #define mmMMEA4_DSM_CNTLB_DEFAULT 0x00000000 1831 #define mmMMEA4_DSM_CNTL2_DEFAULT 0x00000000 1832 #define mmMMEA4_DSM_CNTL2A_DEFAULT 0x00000000 1833 #define mmMMEA4_DSM_CNTL2B_DEFAULT 0x00000000 1834 #define mmMMEA4_CGTT_CLK_CTRL_DEFAULT 0x00000100 1835 #define mmMMEA4_EDC_MODE_DEFAULT 0x00000000 1836 #define mmMMEA4_ERR_STATUS_DEFAULT 0x00000300 1837 #define mmMMEA4_MISC2_DEFAULT 0x00000000 1838 #define mmMMEA4_ADDRDEC_SELECT_DEFAULT 0x00000000 1839 #define mmMMEA4_EDC_CNT3_DEFAULT 0x00000000 1840 1841 1842 // addressBlock: mmhub_pctldec0 1843 #define mmPCTL0_CTRL_DEFAULT 0x00011040 1844 #define mmPCTL0_MMHUB_DEEPSLEEP_IB_DEFAULT 0x00000000 1845 #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 1846 #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT 0x00000000 1847 #define mmPCTL0_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 1848 #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_DEFAULT 0x00000000 1849 #define mmPCTL0_SLICE0_CFG_DAGB_BUSY_DEFAULT 0x00000000 1850 #define mmPCTL0_SLICE0_CFG_DS_ALLOW_DEFAULT 0x00000000 1851 #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 1852 #define mmPCTL0_SLICE1_CFG_DAGB_BUSY_DEFAULT 0x00000000 1853 #define mmPCTL0_SLICE1_CFG_DS_ALLOW_DEFAULT 0x00000000 1854 #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 1855 #define mmPCTL0_SLICE2_CFG_DAGB_BUSY_DEFAULT 0x00000000 1856 #define mmPCTL0_SLICE2_CFG_DS_ALLOW_DEFAULT 0x00000000 1857 #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 1858 #define mmPCTL0_SLICE3_CFG_DAGB_BUSY_DEFAULT 0x00000000 1859 #define mmPCTL0_SLICE3_CFG_DS_ALLOW_DEFAULT 0x00000000 1860 #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 1861 #define mmPCTL0_SLICE4_CFG_DAGB_BUSY_DEFAULT 0x00000000 1862 #define mmPCTL0_SLICE4_CFG_DS_ALLOW_DEFAULT 0x00000000 1863 #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 1864 #define mmPCTL0_UTCL2_MISC_DEFAULT 0x00011000 1865 #define mmPCTL0_SLICE0_MISC_DEFAULT 0x00000800 1866 #define mmPCTL0_SLICE1_MISC_DEFAULT 0x00000800 1867 #define mmPCTL0_SLICE2_MISC_DEFAULT 0x00000800 1868 #define mmPCTL0_SLICE3_MISC_DEFAULT 0x00000800 1869 #define mmPCTL0_SLICE4_MISC_DEFAULT 0x00000800 1870 #define mmPCTL0_UTCL2_RENG_EXECUTE_DEFAULT 0x00000000 1871 #define mmPCTL0_SLICE0_RENG_EXECUTE_DEFAULT 0x00000000 1872 #define mmPCTL0_SLICE1_RENG_EXECUTE_DEFAULT 0x00000000 1873 #define mmPCTL0_SLICE2_RENG_EXECUTE_DEFAULT 0x00000000 1874 #define mmPCTL0_SLICE3_RENG_EXECUTE_DEFAULT 0x00000000 1875 #define mmPCTL0_SLICE4_RENG_EXECUTE_DEFAULT 0x00000000 1876 #define mmPCTL0_UTCL2_RENG_RAM_INDEX_DEFAULT 0x00000000 1877 #define mmPCTL0_UTCL2_RENG_RAM_DATA_DEFAULT 0x00000000 1878 #define mmPCTL0_SLICE0_RENG_RAM_INDEX_DEFAULT 0x00000000 1879 #define mmPCTL0_SLICE0_RENG_RAM_DATA_DEFAULT 0x00000000 1880 #define mmPCTL0_SLICE1_RENG_RAM_INDEX_DEFAULT 0x00000000 1881 #define mmPCTL0_SLICE1_RENG_RAM_DATA_DEFAULT 0x00000000 1882 #define mmPCTL0_SLICE2_RENG_RAM_INDEX_DEFAULT 0x00000000 1883 #define mmPCTL0_SLICE2_RENG_RAM_DATA_DEFAULT 0x00000000 1884 #define mmPCTL0_SLICE3_RENG_RAM_INDEX_DEFAULT 0x00000000 1885 #define mmPCTL0_SLICE3_RENG_RAM_DATA_DEFAULT 0x00000000 1886 #define mmPCTL0_SLICE4_RENG_RAM_INDEX_DEFAULT 0x00000000 1887 #define mmPCTL0_SLICE4_RENG_RAM_DATA_DEFAULT 0x00000000 1888 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 1889 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 1890 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 1891 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 1892 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 1893 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 1894 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 1895 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 1896 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 1897 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 1898 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 1899 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 1900 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 1901 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 1902 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 1903 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 1904 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 1905 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 1906 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 1907 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 1908 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 1909 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 1910 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 1911 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 1912 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 1913 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 1914 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 1915 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 1916 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 1917 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 1918 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 1919 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 1920 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 1921 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 1922 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 1923 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 1924 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 1925 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 1926 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 1927 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 1928 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 1929 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 1930 1931 1932 // addressBlock: mmhub_l1tlb_vml1dec 1933 #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 1934 #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 1935 #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 1936 #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 1937 #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 1938 #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 1939 #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 1940 #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 1941 1942 1943 // addressBlock: mmhub_l1tlb_vml1pldec 1944 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 1945 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 1946 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 1947 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 1948 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 1949 1950 1951 // addressBlock: mmhub_l1tlb_vml1prdec 1952 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 1953 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 1954 1955 1956 // addressBlock: mmhub_utcl2_atcl2dec 1957 #define mmATCL2_0_ATC_L2_CNTL_DEFAULT 0x0001c0c9 1958 #define mmATCL2_0_ATC_L2_CNTL2_DEFAULT 0x00600100 1959 #define mmATCL2_0_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 1960 #define mmATCL2_0_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 1961 #define mmATCL2_0_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 1962 #define mmATCL2_0_ATC_L2_CNTL3_DEFAULT 0x000001f8 1963 #define mmATCL2_0_ATC_L2_STATUS_DEFAULT 0x00000000 1964 #define mmATCL2_0_ATC_L2_STATUS2_DEFAULT 0x00000000 1965 #define mmATCL2_0_ATC_L2_STATUS3_DEFAULT 0x00000000 1966 #define mmATCL2_0_ATC_L2_MISC_CG_DEFAULT 0x00000200 1967 #define mmATCL2_0_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 1968 #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 1969 #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT 0x00000000 1970 #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT 0x00000000 1971 #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT 0x00000000 1972 #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT 0x00000000 1973 #define mmATCL2_0_ATC_L2_CNTL4_DEFAULT 0x00000000 1974 #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000005 1975 1976 1977 // addressBlock: mmhub_utcl2_vml2pfdec 1978 #define mmVML2PF0_VM_L2_CNTL_DEFAULT 0x00080602 1979 #define mmVML2PF0_VM_L2_CNTL2_DEFAULT 0x00000000 1980 #define mmVML2PF0_VM_L2_CNTL3_DEFAULT 0x80100007 1981 #define mmVML2PF0_VM_L2_STATUS_DEFAULT 0x00000000 1982 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 1983 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 1984 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 1985 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc 1986 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 1987 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff 1988 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff 1989 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 1990 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 1991 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 1992 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 1993 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 1994 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 1995 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 1996 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 1997 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 1998 #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 1999 #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 2000 #define mmVML2PF0_VM_L2_CNTL4_DEFAULT 0x000000c1 2001 #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 2002 #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 2003 #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 2004 #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 2005 #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 2006 2007 2008 // addressBlock: mmhub_utcl2_vml2vcdec 2009 #define mmVML2VC0_VM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 2010 #define mmVML2VC0_VM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 2011 #define mmVML2VC0_VM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 2012 #define mmVML2VC0_VM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 2013 #define mmVML2VC0_VM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 2014 #define mmVML2VC0_VM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 2015 #define mmVML2VC0_VM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 2016 #define mmVML2VC0_VM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 2017 #define mmVML2VC0_VM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 2018 #define mmVML2VC0_VM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 2019 #define mmVML2VC0_VM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 2020 #define mmVML2VC0_VM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 2021 #define mmVML2VC0_VM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 2022 #define mmVML2VC0_VM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 2023 #define mmVML2VC0_VM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 2024 #define mmVML2VC0_VM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 2025 #define mmVML2VC0_VM_CONTEXTS_DISABLE_DEFAULT 0x00000000 2026 #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 2027 #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 2028 #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 2029 #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 2030 #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 2031 #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 2032 #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 2033 #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 2034 #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 2035 #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 2036 #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 2037 #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 2038 #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 2039 #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 2040 #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 2041 #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 2042 #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 2043 #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 2044 #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 2045 #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 2046 #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 2047 #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 2048 #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 2049 #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 2050 #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 2051 #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 2052 #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 2053 #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 2054 #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 2055 #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 2056 #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 2057 #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 2058 #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 2059 #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 2060 #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 2061 #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 2062 #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 2063 #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 2064 #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 2065 #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 2066 #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 2067 #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 2068 #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 2069 #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 2070 #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 2071 #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 2072 #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 2073 #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 2074 #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 2075 #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 2076 #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 2077 #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 2078 #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 2079 #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 2080 #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 2081 #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 2082 #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 2083 #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 2084 #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 2085 #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 2086 #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 2087 #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 2088 #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 2089 #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 2090 #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 2091 #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 2092 #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 2093 #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 2094 #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 2095 #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 2096 #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 2097 #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 2098 #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 2099 #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 2100 #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 2101 #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 2102 #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 2103 #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 2104 #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 2105 #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 2106 #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 2107 #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 2108 #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 2109 #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 2110 #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 2111 #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 2112 #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 2113 #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 2114 #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 2115 #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 2116 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2117 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2118 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2119 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2120 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2121 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2122 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2123 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2124 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2125 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2126 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2127 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2128 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2129 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2130 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2131 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2132 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2133 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2134 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2135 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2136 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2137 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2138 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2139 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2140 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2141 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2142 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2143 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2144 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2145 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2146 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 2147 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 2148 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2149 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2150 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2151 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2152 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2153 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2154 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2155 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2156 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2157 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2158 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2159 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2160 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2161 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2162 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2163 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2164 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2165 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2166 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2167 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2168 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2169 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2170 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2171 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2172 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2173 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2174 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2175 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2176 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2177 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2178 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 2179 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 2180 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2181 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2182 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2183 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2184 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2185 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2186 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2187 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2188 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2189 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2190 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2191 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2192 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2193 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2194 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2195 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2196 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2197 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2198 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2199 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2200 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2201 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2202 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2203 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2204 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2205 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2206 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2207 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2208 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2209 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2210 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 2211 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 2212 2213 2214 // addressBlock: mmhub_utcl2_vmsharedpfdec 2215 #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_DEFAULT 0x00000000 2216 #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 2217 #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 2218 #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_DEFAULT 0x00000008 2219 #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 2220 #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 2221 #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 2222 #define mmVMSHAREDPF0_MC_VM_FB_OFFSET_DEFAULT 0x00000000 2223 #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 2224 #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 2225 #define mmVMSHAREDPF0_MC_VM_STEERING_DEFAULT 0x00000001 2226 #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 2227 #define mmVMSHAREDPF0_MC_MEM_POWER_LS_DEFAULT 0x00000208 2228 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 2229 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 2230 #define mmVMSHAREDPF0_MC_VM_APT_CNTL_DEFAULT 0x00000000 2231 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 2232 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff 2233 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 2234 #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_DEFAULT 0x00000000 2235 #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_DEFAULT 0x00000000 2236 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT 0x00000000 2237 2238 2239 // addressBlock: mmhub_utcl2_vmsharedvcdec 2240 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 2241 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 2242 #define mmVMSHAREDVC0_MC_VM_AGP_TOP_DEFAULT 0x00000000 2243 #define mmVMSHAREDVC0_MC_VM_AGP_BOT_DEFAULT 0x00000000 2244 #define mmVMSHAREDVC0_MC_VM_AGP_BASE_DEFAULT 0x00000000 2245 #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 2246 #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 2247 #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 2248 2249 2250 // addressBlock: mmhub_utcl2_vmsharedhvdec 2251 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 2252 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 2253 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 2254 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 2255 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 2256 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 2257 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 2258 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 2259 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 2260 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 2261 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 2262 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 2263 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 2264 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 2265 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 2266 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 2267 #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 2268 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 2269 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 2270 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 2271 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 2272 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 2273 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 2274 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 2275 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 2276 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 2277 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 2278 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 2279 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 2280 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 2281 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 2282 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 2283 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 2284 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 2285 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 2286 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 2287 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 2288 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 2289 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 2290 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 2291 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 2292 #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 2293 #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 2294 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_DEFAULT 0x00000000 2295 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 2296 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 2297 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 2298 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 2299 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 2300 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 2301 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 2302 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 2303 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 2304 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 2305 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 2306 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 2307 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 2308 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 2309 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 2310 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 2311 #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 2312 #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 2313 #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT 0x00000000 2314 2315 2316 // addressBlock: mmhub_utcl2_atcl2pfcntrdec 2317 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 2318 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 2319 2320 2321 // addressBlock: mmhub_utcl2_atcl2pfcntldec 2322 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 2323 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 2324 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 2325 2326 2327 // addressBlock: mmhub_utcl2_vml2pldec 2328 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 2329 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 2330 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 2331 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 2332 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 2333 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 2334 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 2335 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 2336 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 2337 2338 2339 // addressBlock: mmhub_utcl2_vml2prdec 2340 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 2341 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 2342 2343 2344 // addressBlock: mmhub_dagb_dagbdec5 2345 #define mmDAGB5_RDCLI0_DEFAULT 0xfe5fe0f9 2346 #define mmDAGB5_RDCLI1_DEFAULT 0xfe5fe0f9 2347 #define mmDAGB5_RDCLI2_DEFAULT 0xfe5fe0f9 2348 #define mmDAGB5_RDCLI3_DEFAULT 0xfe5fe0f9 2349 #define mmDAGB5_RDCLI4_DEFAULT 0xfe5fe0f9 2350 #define mmDAGB5_RDCLI5_DEFAULT 0xfe5fe0f9 2351 #define mmDAGB5_RDCLI6_DEFAULT 0xfe5fe0f9 2352 #define mmDAGB5_RDCLI7_DEFAULT 0xfe5fe0f9 2353 #define mmDAGB5_RDCLI8_DEFAULT 0xfe5fe0f9 2354 #define mmDAGB5_RDCLI9_DEFAULT 0xfe5fe0f9 2355 #define mmDAGB5_RDCLI10_DEFAULT 0xfe5fe0f9 2356 #define mmDAGB5_RDCLI11_DEFAULT 0xfe5fe0f9 2357 #define mmDAGB5_RDCLI12_DEFAULT 0xfe5fe0f9 2358 #define mmDAGB5_RDCLI13_DEFAULT 0xfe5fe0f9 2359 #define mmDAGB5_RDCLI14_DEFAULT 0xfe5fe0f9 2360 #define mmDAGB5_RDCLI15_DEFAULT 0xfe5fe0f9 2361 #define mmDAGB5_RD_CNTL_DEFAULT 0x03527df8 2362 #define mmDAGB5_RD_GMI_CNTL_DEFAULT 0x00003045 2363 #define mmDAGB5_RD_ADDR_DAGB_DEFAULT 0x00000039 2364 #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 2365 #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 2366 #define mmDAGB5_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2367 #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2368 #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2369 #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 2370 #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 2371 #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 2372 #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 2373 #define mmDAGB5_RD_VC0_CNTL_DEFAULT 0xff2ff082 2374 #define mmDAGB5_RD_VC1_CNTL_DEFAULT 0xff2ff082 2375 #define mmDAGB5_RD_VC2_CNTL_DEFAULT 0xff2ff082 2376 #define mmDAGB5_RD_VC3_CNTL_DEFAULT 0xff2ff082 2377 #define mmDAGB5_RD_VC4_CNTL_DEFAULT 0xff2ff082 2378 #define mmDAGB5_RD_VC5_CNTL_DEFAULT 0xff2ff082 2379 #define mmDAGB5_RD_VC6_CNTL_DEFAULT 0xff2ff082 2380 #define mmDAGB5_RD_VC7_CNTL_DEFAULT 0xff2ff082 2381 #define mmDAGB5_RD_CNTL_MISC_DEFAULT 0x69a0e408 2382 #define mmDAGB5_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 2383 #define mmDAGB5_RDCLI_ASK_PENDING_DEFAULT 0x00000000 2384 #define mmDAGB5_RDCLI_GO_PENDING_DEFAULT 0x00000000 2385 #define mmDAGB5_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 2386 #define mmDAGB5_RDCLI_TLB_PENDING_DEFAULT 0x00000000 2387 #define mmDAGB5_RDCLI_OARB_PENDING_DEFAULT 0x00000000 2388 #define mmDAGB5_RDCLI_OSD_PENDING_DEFAULT 0x00000000 2389 #define mmDAGB5_WRCLI0_DEFAULT 0xfe5fe0f9 2390 #define mmDAGB5_WRCLI1_DEFAULT 0xfe5fe0f9 2391 #define mmDAGB5_WRCLI2_DEFAULT 0xfe5fe0f9 2392 #define mmDAGB5_WRCLI3_DEFAULT 0xfe5fe0f9 2393 #define mmDAGB5_WRCLI4_DEFAULT 0xfe5fe0f9 2394 #define mmDAGB5_WRCLI5_DEFAULT 0xfe5fe0f9 2395 #define mmDAGB5_WRCLI6_DEFAULT 0xfe5fe0f9 2396 #define mmDAGB5_WRCLI7_DEFAULT 0xfe5fe0f9 2397 #define mmDAGB5_WRCLI8_DEFAULT 0xfe5fe0f9 2398 #define mmDAGB5_WRCLI9_DEFAULT 0xfe5fe0f9 2399 #define mmDAGB5_WRCLI10_DEFAULT 0xfe5fe0f9 2400 #define mmDAGB5_WRCLI11_DEFAULT 0xfe5fe0f9 2401 #define mmDAGB5_WRCLI12_DEFAULT 0xfe5fe0f9 2402 #define mmDAGB5_WRCLI13_DEFAULT 0xfe5fe0f9 2403 #define mmDAGB5_WRCLI14_DEFAULT 0xfe5fe0f9 2404 #define mmDAGB5_WRCLI15_DEFAULT 0xfe5fe0f9 2405 #define mmDAGB5_WR_CNTL_DEFAULT 0x03527df8 2406 #define mmDAGB5_WR_GMI_CNTL_DEFAULT 0x00003045 2407 #define mmDAGB5_WR_ADDR_DAGB_DEFAULT 0x00000039 2408 #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 2409 #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 2410 #define mmDAGB5_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2411 #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2412 #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2413 #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 2414 #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 2415 #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 2416 #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 2417 #define mmDAGB5_WR_DATA_DAGB_DEFAULT 0x00000001 2418 #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 2419 #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 2420 #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 2421 #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 2422 #define mmDAGB5_WR_VC0_CNTL_DEFAULT 0xff2ff082 2423 #define mmDAGB5_WR_VC1_CNTL_DEFAULT 0xff2ff082 2424 #define mmDAGB5_WR_VC2_CNTL_DEFAULT 0xff2ff082 2425 #define mmDAGB5_WR_VC3_CNTL_DEFAULT 0xff2ff082 2426 #define mmDAGB5_WR_VC4_CNTL_DEFAULT 0xff2ff082 2427 #define mmDAGB5_WR_VC5_CNTL_DEFAULT 0xff2ff082 2428 #define mmDAGB5_WR_VC6_CNTL_DEFAULT 0xff2ff082 2429 #define mmDAGB5_WR_VC7_CNTL_DEFAULT 0xff2ff082 2430 #define mmDAGB5_WR_CNTL_MISC_DEFAULT 0x69a0e408 2431 #define mmDAGB5_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 2432 #define mmDAGB5_WR_DATA_CREDIT_DEFAULT 0x60606070 2433 #define mmDAGB5_WR_MISC_CREDIT_DEFAULT 0x0078dc88 2434 #define mmDAGB5_WRCLI_ASK_PENDING_DEFAULT 0x00000000 2435 #define mmDAGB5_WRCLI_GO_PENDING_DEFAULT 0x00000000 2436 #define mmDAGB5_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 2437 #define mmDAGB5_WRCLI_TLB_PENDING_DEFAULT 0x00000000 2438 #define mmDAGB5_WRCLI_OARB_PENDING_DEFAULT 0x00000000 2439 #define mmDAGB5_WRCLI_OSD_PENDING_DEFAULT 0x00000000 2440 #define mmDAGB5_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 2441 #define mmDAGB5_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 2442 #define mmDAGB5_DAGB_DLY_DEFAULT 0x00000000 2443 #define mmDAGB5_CNTL_MISC_DEFAULT 0xcf7c1ffa 2444 #define mmDAGB5_CNTL_MISC2_DEFAULT 0x003c0000 2445 #define mmDAGB5_FIFO_EMPTY_DEFAULT 0x00ffffff 2446 #define mmDAGB5_FIFO_FULL_DEFAULT 0x00000000 2447 #define mmDAGB5_WR_CREDITS_FULL_DEFAULT 0x1fffffff 2448 #define mmDAGB5_RD_CREDITS_FULL_DEFAULT 0x0003ffff 2449 #define mmDAGB5_PERFCOUNTER_LO_DEFAULT 0x00000000 2450 #define mmDAGB5_PERFCOUNTER_HI_DEFAULT 0x00000000 2451 #define mmDAGB5_PERFCOUNTER0_CFG_DEFAULT 0x00000000 2452 #define mmDAGB5_PERFCOUNTER1_CFG_DEFAULT 0x00000000 2453 #define mmDAGB5_PERFCOUNTER2_CFG_DEFAULT 0x00000000 2454 #define mmDAGB5_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 2455 #define mmDAGB5_RESERVE0_DEFAULT 0xffffffff 2456 #define mmDAGB5_RESERVE1_DEFAULT 0xffffffff 2457 #define mmDAGB5_RESERVE2_DEFAULT 0xffffffff 2458 #define mmDAGB5_RESERVE3_DEFAULT 0xffffffff 2459 #define mmDAGB5_RESERVE4_DEFAULT 0xffffffff 2460 #define mmDAGB5_RESERVE5_DEFAULT 0xffffffff 2461 #define mmDAGB5_RESERVE6_DEFAULT 0xffffffff 2462 #define mmDAGB5_RESERVE7_DEFAULT 0xffffffff 2463 #define mmDAGB5_RESERVE8_DEFAULT 0xffffffff 2464 #define mmDAGB5_RESERVE9_DEFAULT 0xffffffff 2465 #define mmDAGB5_RESERVE10_DEFAULT 0xffffffff 2466 #define mmDAGB5_RESERVE11_DEFAULT 0xffffffff 2467 #define mmDAGB5_RESERVE12_DEFAULT 0xffffffff 2468 #define mmDAGB5_RESERVE13_DEFAULT 0xffffffff 2469 2470 2471 // addressBlock: mmhub_dagb_dagbdec6 2472 #define mmDAGB6_RDCLI0_DEFAULT 0xfe5fe0f9 2473 #define mmDAGB6_RDCLI1_DEFAULT 0xfe5fe0f9 2474 #define mmDAGB6_RDCLI2_DEFAULT 0xfe5fe0f9 2475 #define mmDAGB6_RDCLI3_DEFAULT 0xfe5fe0f9 2476 #define mmDAGB6_RDCLI4_DEFAULT 0xfe5fe0f9 2477 #define mmDAGB6_RDCLI5_DEFAULT 0xfe5fe0f9 2478 #define mmDAGB6_RDCLI6_DEFAULT 0xfe5fe0f9 2479 #define mmDAGB6_RDCLI7_DEFAULT 0xfe5fe0f9 2480 #define mmDAGB6_RDCLI8_DEFAULT 0xfe5fe0f9 2481 #define mmDAGB6_RDCLI9_DEFAULT 0xfe5fe0f9 2482 #define mmDAGB6_RDCLI10_DEFAULT 0xfe5fe0f9 2483 #define mmDAGB6_RDCLI11_DEFAULT 0xfe5fe0f9 2484 #define mmDAGB6_RDCLI12_DEFAULT 0xfe5fe0f9 2485 #define mmDAGB6_RDCLI13_DEFAULT 0xfe5fe0f9 2486 #define mmDAGB6_RDCLI14_DEFAULT 0xfe5fe0f9 2487 #define mmDAGB6_RDCLI15_DEFAULT 0xfe5fe0f9 2488 #define mmDAGB6_RD_CNTL_DEFAULT 0x03527df8 2489 #define mmDAGB6_RD_GMI_CNTL_DEFAULT 0x00003045 2490 #define mmDAGB6_RD_ADDR_DAGB_DEFAULT 0x00000039 2491 #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 2492 #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 2493 #define mmDAGB6_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2494 #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2495 #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2496 #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 2497 #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 2498 #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 2499 #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 2500 #define mmDAGB6_RD_VC0_CNTL_DEFAULT 0xff2ff082 2501 #define mmDAGB6_RD_VC1_CNTL_DEFAULT 0xff2ff082 2502 #define mmDAGB6_RD_VC2_CNTL_DEFAULT 0xff2ff082 2503 #define mmDAGB6_RD_VC3_CNTL_DEFAULT 0xff2ff082 2504 #define mmDAGB6_RD_VC4_CNTL_DEFAULT 0xff2ff082 2505 #define mmDAGB6_RD_VC5_CNTL_DEFAULT 0xff2ff082 2506 #define mmDAGB6_RD_VC6_CNTL_DEFAULT 0xff2ff082 2507 #define mmDAGB6_RD_VC7_CNTL_DEFAULT 0xff2ff082 2508 #define mmDAGB6_RD_CNTL_MISC_DEFAULT 0x69a0e408 2509 #define mmDAGB6_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 2510 #define mmDAGB6_RDCLI_ASK_PENDING_DEFAULT 0x00000000 2511 #define mmDAGB6_RDCLI_GO_PENDING_DEFAULT 0x00000000 2512 #define mmDAGB6_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 2513 #define mmDAGB6_RDCLI_TLB_PENDING_DEFAULT 0x00000000 2514 #define mmDAGB6_RDCLI_OARB_PENDING_DEFAULT 0x00000000 2515 #define mmDAGB6_RDCLI_OSD_PENDING_DEFAULT 0x00000000 2516 #define mmDAGB6_WRCLI0_DEFAULT 0xfe5fe0f9 2517 #define mmDAGB6_WRCLI1_DEFAULT 0xfe5fe0f9 2518 #define mmDAGB6_WRCLI2_DEFAULT 0xfe5fe0f9 2519 #define mmDAGB6_WRCLI3_DEFAULT 0xfe5fe0f9 2520 #define mmDAGB6_WRCLI4_DEFAULT 0xfe5fe0f9 2521 #define mmDAGB6_WRCLI5_DEFAULT 0xfe5fe0f9 2522 #define mmDAGB6_WRCLI6_DEFAULT 0xfe5fe0f9 2523 #define mmDAGB6_WRCLI7_DEFAULT 0xfe5fe0f9 2524 #define mmDAGB6_WRCLI8_DEFAULT 0xfe5fe0f9 2525 #define mmDAGB6_WRCLI9_DEFAULT 0xfe5fe0f9 2526 #define mmDAGB6_WRCLI10_DEFAULT 0xfe5fe0f9 2527 #define mmDAGB6_WRCLI11_DEFAULT 0xfe5fe0f9 2528 #define mmDAGB6_WRCLI12_DEFAULT 0xfe5fe0f9 2529 #define mmDAGB6_WRCLI13_DEFAULT 0xfe5fe0f9 2530 #define mmDAGB6_WRCLI14_DEFAULT 0xfe5fe0f9 2531 #define mmDAGB6_WRCLI15_DEFAULT 0xfe5fe0f9 2532 #define mmDAGB6_WR_CNTL_DEFAULT 0x03527df8 2533 #define mmDAGB6_WR_GMI_CNTL_DEFAULT 0x00003045 2534 #define mmDAGB6_WR_ADDR_DAGB_DEFAULT 0x00000039 2535 #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 2536 #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 2537 #define mmDAGB6_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2538 #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2539 #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2540 #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 2541 #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 2542 #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 2543 #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 2544 #define mmDAGB6_WR_DATA_DAGB_DEFAULT 0x00000001 2545 #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 2546 #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 2547 #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 2548 #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 2549 #define mmDAGB6_WR_VC0_CNTL_DEFAULT 0xff2ff082 2550 #define mmDAGB6_WR_VC1_CNTL_DEFAULT 0xff2ff082 2551 #define mmDAGB6_WR_VC2_CNTL_DEFAULT 0xff2ff082 2552 #define mmDAGB6_WR_VC3_CNTL_DEFAULT 0xff2ff082 2553 #define mmDAGB6_WR_VC4_CNTL_DEFAULT 0xff2ff082 2554 #define mmDAGB6_WR_VC5_CNTL_DEFAULT 0xff2ff082 2555 #define mmDAGB6_WR_VC6_CNTL_DEFAULT 0xff2ff082 2556 #define mmDAGB6_WR_VC7_CNTL_DEFAULT 0xff2ff082 2557 #define mmDAGB6_WR_CNTL_MISC_DEFAULT 0x69a0e408 2558 #define mmDAGB6_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 2559 #define mmDAGB6_WR_DATA_CREDIT_DEFAULT 0x60606070 2560 #define mmDAGB6_WR_MISC_CREDIT_DEFAULT 0x0078dc88 2561 #define mmDAGB6_WRCLI_ASK_PENDING_DEFAULT 0x00000000 2562 #define mmDAGB6_WRCLI_GO_PENDING_DEFAULT 0x00000000 2563 #define mmDAGB6_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 2564 #define mmDAGB6_WRCLI_TLB_PENDING_DEFAULT 0x00000000 2565 #define mmDAGB6_WRCLI_OARB_PENDING_DEFAULT 0x00000000 2566 #define mmDAGB6_WRCLI_OSD_PENDING_DEFAULT 0x00000000 2567 #define mmDAGB6_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 2568 #define mmDAGB6_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 2569 #define mmDAGB6_DAGB_DLY_DEFAULT 0x00000000 2570 #define mmDAGB6_CNTL_MISC_DEFAULT 0xcf7c1ffa 2571 #define mmDAGB6_CNTL_MISC2_DEFAULT 0x003c0000 2572 #define mmDAGB6_FIFO_EMPTY_DEFAULT 0x00ffffff 2573 #define mmDAGB6_FIFO_FULL_DEFAULT 0x00000000 2574 #define mmDAGB6_WR_CREDITS_FULL_DEFAULT 0x1fffffff 2575 #define mmDAGB6_RD_CREDITS_FULL_DEFAULT 0x0003ffff 2576 #define mmDAGB6_PERFCOUNTER_LO_DEFAULT 0x00000000 2577 #define mmDAGB6_PERFCOUNTER_HI_DEFAULT 0x00000000 2578 #define mmDAGB6_PERFCOUNTER0_CFG_DEFAULT 0x00000000 2579 #define mmDAGB6_PERFCOUNTER1_CFG_DEFAULT 0x00000000 2580 #define mmDAGB6_PERFCOUNTER2_CFG_DEFAULT 0x00000000 2581 #define mmDAGB6_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 2582 #define mmDAGB6_RESERVE0_DEFAULT 0xffffffff 2583 #define mmDAGB6_RESERVE1_DEFAULT 0xffffffff 2584 #define mmDAGB6_RESERVE2_DEFAULT 0xffffffff 2585 #define mmDAGB6_RESERVE3_DEFAULT 0xffffffff 2586 #define mmDAGB6_RESERVE4_DEFAULT 0xffffffff 2587 #define mmDAGB6_RESERVE5_DEFAULT 0xffffffff 2588 #define mmDAGB6_RESERVE6_DEFAULT 0xffffffff 2589 #define mmDAGB6_RESERVE7_DEFAULT 0xffffffff 2590 #define mmDAGB6_RESERVE8_DEFAULT 0xffffffff 2591 #define mmDAGB6_RESERVE9_DEFAULT 0xffffffff 2592 #define mmDAGB6_RESERVE10_DEFAULT 0xffffffff 2593 #define mmDAGB6_RESERVE11_DEFAULT 0xffffffff 2594 #define mmDAGB6_RESERVE12_DEFAULT 0xffffffff 2595 #define mmDAGB6_RESERVE13_DEFAULT 0xffffffff 2596 2597 2598 // addressBlock: mmhub_dagb_dagbdec7 2599 #define mmDAGB7_RDCLI0_DEFAULT 0xfe5fe0f9 2600 #define mmDAGB7_RDCLI1_DEFAULT 0xfe5fe0f9 2601 #define mmDAGB7_RDCLI2_DEFAULT 0xfe5fe0f9 2602 #define mmDAGB7_RDCLI3_DEFAULT 0xfe5fe0f9 2603 #define mmDAGB7_RDCLI4_DEFAULT 0xfe5fe0f9 2604 #define mmDAGB7_RDCLI5_DEFAULT 0xfe5fe0f9 2605 #define mmDAGB7_RDCLI6_DEFAULT 0xfe5fe0f9 2606 #define mmDAGB7_RDCLI7_DEFAULT 0xfe5fe0f9 2607 #define mmDAGB7_RDCLI8_DEFAULT 0xfe5fe0f9 2608 #define mmDAGB7_RDCLI9_DEFAULT 0xfe5fe0f9 2609 #define mmDAGB7_RDCLI10_DEFAULT 0xfe5fe0f9 2610 #define mmDAGB7_RDCLI11_DEFAULT 0xfe5fe0f9 2611 #define mmDAGB7_RDCLI12_DEFAULT 0xfe5fe0f9 2612 #define mmDAGB7_RDCLI13_DEFAULT 0xfe5fe0f9 2613 #define mmDAGB7_RDCLI14_DEFAULT 0xfe5fe0f9 2614 #define mmDAGB7_RDCLI15_DEFAULT 0xfe5fe0f9 2615 #define mmDAGB7_RD_CNTL_DEFAULT 0x03527df8 2616 #define mmDAGB7_RD_GMI_CNTL_DEFAULT 0x00003045 2617 #define mmDAGB7_RD_ADDR_DAGB_DEFAULT 0x00000039 2618 #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 2619 #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 2620 #define mmDAGB7_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2621 #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2622 #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 2623 #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 2624 #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 2625 #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 2626 #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 2627 #define mmDAGB7_RD_VC0_CNTL_DEFAULT 0xff2ff082 2628 #define mmDAGB7_RD_VC1_CNTL_DEFAULT 0xff2ff082 2629 #define mmDAGB7_RD_VC2_CNTL_DEFAULT 0xff2ff082 2630 #define mmDAGB7_RD_VC3_CNTL_DEFAULT 0xff2ff082 2631 #define mmDAGB7_RD_VC4_CNTL_DEFAULT 0xff2ff082 2632 #define mmDAGB7_RD_VC5_CNTL_DEFAULT 0xff2ff082 2633 #define mmDAGB7_RD_VC6_CNTL_DEFAULT 0xff2ff082 2634 #define mmDAGB7_RD_VC7_CNTL_DEFAULT 0xff2ff082 2635 #define mmDAGB7_RD_CNTL_MISC_DEFAULT 0x69a0e408 2636 #define mmDAGB7_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 2637 #define mmDAGB7_RDCLI_ASK_PENDING_DEFAULT 0x00000000 2638 #define mmDAGB7_RDCLI_GO_PENDING_DEFAULT 0x00000000 2639 #define mmDAGB7_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 2640 #define mmDAGB7_RDCLI_TLB_PENDING_DEFAULT 0x00000000 2641 #define mmDAGB7_RDCLI_OARB_PENDING_DEFAULT 0x00000000 2642 #define mmDAGB7_RDCLI_OSD_PENDING_DEFAULT 0x00000000 2643 #define mmDAGB7_WRCLI0_DEFAULT 0xfe5fe0f9 2644 #define mmDAGB7_WRCLI1_DEFAULT 0xfe5fe0f9 2645 #define mmDAGB7_WRCLI2_DEFAULT 0xfe5fe0f9 2646 #define mmDAGB7_WRCLI3_DEFAULT 0xfe5fe0f9 2647 #define mmDAGB7_WRCLI4_DEFAULT 0xfe5fe0f9 2648 #define mmDAGB7_WRCLI5_DEFAULT 0xfe5fe0f9 2649 #define mmDAGB7_WRCLI6_DEFAULT 0xfe5fe0f9 2650 #define mmDAGB7_WRCLI7_DEFAULT 0xfe5fe0f9 2651 #define mmDAGB7_WRCLI8_DEFAULT 0xfe5fe0f9 2652 #define mmDAGB7_WRCLI9_DEFAULT 0xfe5fe0f9 2653 #define mmDAGB7_WRCLI10_DEFAULT 0xfe5fe0f9 2654 #define mmDAGB7_WRCLI11_DEFAULT 0xfe5fe0f9 2655 #define mmDAGB7_WRCLI12_DEFAULT 0xfe5fe0f9 2656 #define mmDAGB7_WRCLI13_DEFAULT 0xfe5fe0f9 2657 #define mmDAGB7_WRCLI14_DEFAULT 0xfe5fe0f9 2658 #define mmDAGB7_WRCLI15_DEFAULT 0xfe5fe0f9 2659 #define mmDAGB7_WR_CNTL_DEFAULT 0x03527df8 2660 #define mmDAGB7_WR_GMI_CNTL_DEFAULT 0x00003045 2661 #define mmDAGB7_WR_ADDR_DAGB_DEFAULT 0x00000039 2662 #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 2663 #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 2664 #define mmDAGB7_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2665 #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2666 #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 2667 #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 2668 #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 2669 #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 2670 #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 2671 #define mmDAGB7_WR_DATA_DAGB_DEFAULT 0x00000001 2672 #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 2673 #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 2674 #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 2675 #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 2676 #define mmDAGB7_WR_VC0_CNTL_DEFAULT 0xff2ff082 2677 #define mmDAGB7_WR_VC1_CNTL_DEFAULT 0xff2ff082 2678 #define mmDAGB7_WR_VC2_CNTL_DEFAULT 0xff2ff082 2679 #define mmDAGB7_WR_VC3_CNTL_DEFAULT 0xff2ff082 2680 #define mmDAGB7_WR_VC4_CNTL_DEFAULT 0xff2ff082 2681 #define mmDAGB7_WR_VC5_CNTL_DEFAULT 0xff2ff082 2682 #define mmDAGB7_WR_VC6_CNTL_DEFAULT 0xff2ff082 2683 #define mmDAGB7_WR_VC7_CNTL_DEFAULT 0xff2ff082 2684 #define mmDAGB7_WR_CNTL_MISC_DEFAULT 0x69a0e408 2685 #define mmDAGB7_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 2686 #define mmDAGB7_WR_DATA_CREDIT_DEFAULT 0x60606070 2687 #define mmDAGB7_WR_MISC_CREDIT_DEFAULT 0x0078dc88 2688 #define mmDAGB7_WRCLI_ASK_PENDING_DEFAULT 0x00000000 2689 #define mmDAGB7_WRCLI_GO_PENDING_DEFAULT 0x00000000 2690 #define mmDAGB7_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 2691 #define mmDAGB7_WRCLI_TLB_PENDING_DEFAULT 0x00000000 2692 #define mmDAGB7_WRCLI_OARB_PENDING_DEFAULT 0x00000000 2693 #define mmDAGB7_WRCLI_OSD_PENDING_DEFAULT 0x00000000 2694 #define mmDAGB7_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 2695 #define mmDAGB7_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 2696 #define mmDAGB7_DAGB_DLY_DEFAULT 0x00000000 2697 #define mmDAGB7_CNTL_MISC_DEFAULT 0xcf7c1ffa 2698 #define mmDAGB7_CNTL_MISC2_DEFAULT 0x003c0000 2699 #define mmDAGB7_FIFO_EMPTY_DEFAULT 0x00ffffff 2700 #define mmDAGB7_FIFO_FULL_DEFAULT 0x00000000 2701 #define mmDAGB7_WR_CREDITS_FULL_DEFAULT 0x1fffffff 2702 #define mmDAGB7_RD_CREDITS_FULL_DEFAULT 0x0003ffff 2703 #define mmDAGB7_PERFCOUNTER_LO_DEFAULT 0x00000000 2704 #define mmDAGB7_PERFCOUNTER_HI_DEFAULT 0x00000000 2705 #define mmDAGB7_PERFCOUNTER0_CFG_DEFAULT 0x00000000 2706 #define mmDAGB7_PERFCOUNTER1_CFG_DEFAULT 0x00000000 2707 #define mmDAGB7_PERFCOUNTER2_CFG_DEFAULT 0x00000000 2708 #define mmDAGB7_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 2709 #define mmDAGB7_RESERVE0_DEFAULT 0xffffffff 2710 #define mmDAGB7_RESERVE1_DEFAULT 0xffffffff 2711 #define mmDAGB7_RESERVE2_DEFAULT 0xffffffff 2712 #define mmDAGB7_RESERVE3_DEFAULT 0xffffffff 2713 #define mmDAGB7_RESERVE4_DEFAULT 0xffffffff 2714 #define mmDAGB7_RESERVE5_DEFAULT 0xffffffff 2715 #define mmDAGB7_RESERVE6_DEFAULT 0xffffffff 2716 #define mmDAGB7_RESERVE7_DEFAULT 0xffffffff 2717 #define mmDAGB7_RESERVE8_DEFAULT 0xffffffff 2718 #define mmDAGB7_RESERVE9_DEFAULT 0xffffffff 2719 #define mmDAGB7_RESERVE10_DEFAULT 0xffffffff 2720 #define mmDAGB7_RESERVE11_DEFAULT 0xffffffff 2721 #define mmDAGB7_RESERVE12_DEFAULT 0xffffffff 2722 #define mmDAGB7_RESERVE13_DEFAULT 0xffffffff 2723 2724 2725 // addressBlock: mmhub_ea_mmeadec5 2726 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 2727 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 2728 #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 2729 #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 2730 #define mmMMEA5_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 2731 #define mmMMEA5_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 2732 #define mmMMEA5_DRAM_RD_LAZY_DEFAULT 0x78000924 2733 #define mmMMEA5_DRAM_WR_LAZY_DEFAULT 0x78000924 2734 #define mmMMEA5_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 2735 #define mmMMEA5_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 2736 #define mmMMEA5_DRAM_PAGE_BURST_DEFAULT 0x20002000 2737 #define mmMMEA5_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 2738 #define mmMMEA5_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 2739 #define mmMMEA5_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 2740 #define mmMMEA5_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 2741 #define mmMMEA5_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 2742 #define mmMMEA5_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 2743 #define mmMMEA5_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 2744 #define mmMMEA5_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 2745 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2746 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2747 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2748 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2749 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2750 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2751 #define mmMMEA5_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 2752 #define mmMMEA5_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 2753 #define mmMMEA5_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 2754 #define mmMMEA5_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 2755 #define mmMMEA5_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 2756 #define mmMMEA5_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 2757 #define mmMMEA5_GMI_RD_LAZY_DEFAULT 0x78000924 2758 #define mmMMEA5_GMI_WR_LAZY_DEFAULT 0x78000924 2759 #define mmMMEA5_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 2760 #define mmMMEA5_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 2761 #define mmMMEA5_GMI_PAGE_BURST_DEFAULT 0x20002000 2762 #define mmMMEA5_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 2763 #define mmMMEA5_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 2764 #define mmMMEA5_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 2765 #define mmMMEA5_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 2766 #define mmMMEA5_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 2767 #define mmMMEA5_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 2768 #define mmMMEA5_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 2769 #define mmMMEA5_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 2770 #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 2771 #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 2772 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2773 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2774 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2775 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2776 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2777 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2778 #define mmMMEA5_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 2779 #define mmMMEA5_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 2780 #define mmMMEA5_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 2781 #define mmMMEA5_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 2782 #define mmMMEA5_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 2783 #define mmMMEA5_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 2784 #define mmMMEA5_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 2785 #define mmMMEA5_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 2786 #define mmMMEA5_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 2787 #define mmMMEA5_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 2788 #define mmMMEA5_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 2789 #define mmMMEA5_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 2790 #define mmMMEA5_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 2791 #define mmMMEA5_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 2792 #define mmMMEA5_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 2793 #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 2794 #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 2795 #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 2796 #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 2797 #define mmMMEA5_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 2798 #define mmMMEA5_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 2799 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 2800 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 2801 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 2802 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 2803 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 2804 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 2805 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 2806 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 2807 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 2808 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 2809 #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 2810 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 2811 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 2812 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 2813 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 2814 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 2815 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 2816 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 2817 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 2818 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 2819 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 2820 #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 2821 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 2822 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 2823 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 2824 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 2825 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 2826 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 2827 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 2828 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 2829 #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 2830 #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 2831 #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 2832 #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 2833 #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 2834 #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 2835 #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 2836 #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 2837 #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 2838 #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 2839 #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 2840 #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 2841 #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 2842 #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 2843 #define mmMMEA5_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 2844 #define mmMMEA5_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 2845 #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 2846 #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 2847 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 2848 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 2849 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 2850 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 2851 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 2852 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 2853 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 2854 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 2855 #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 2856 #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 2857 #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 2858 #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 2859 #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 2860 #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 2861 #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 2862 #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 2863 #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 2864 #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 2865 #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 2866 #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 2867 #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 2868 #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 2869 #define mmMMEA5_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 2870 #define mmMMEA5_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 2871 #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 2872 #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 2873 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 2874 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 2875 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 2876 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 2877 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 2878 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 2879 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 2880 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 2881 #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 2882 #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 2883 #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 2884 #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 2885 #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 2886 #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 2887 #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 2888 #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 2889 #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 2890 #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 2891 #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 2892 #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 2893 #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 2894 #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 2895 #define mmMMEA5_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 2896 #define mmMMEA5_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 2897 #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 2898 #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 2899 #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 2900 #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 2901 #define mmMMEA5_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 2902 #define mmMMEA5_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 2903 #define mmMMEA5_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 2904 #define mmMMEA5_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 2905 #define mmMMEA5_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 2906 #define mmMMEA5_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 2907 #define mmMMEA5_IO_GROUP_BURST_DEFAULT 0x1f031f03 2908 #define mmMMEA5_IO_RD_PRI_AGE_DEFAULT 0x00db6249 2909 #define mmMMEA5_IO_WR_PRI_AGE_DEFAULT 0x00db6249 2910 #define mmMMEA5_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 2911 #define mmMMEA5_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 2912 #define mmMMEA5_IO_RD_PRI_FIXED_DEFAULT 0x00000924 2913 #define mmMMEA5_IO_WR_PRI_FIXED_DEFAULT 0x00000924 2914 #define mmMMEA5_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 2915 #define mmMMEA5_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 2916 #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 2917 #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 2918 #define mmMMEA5_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2919 #define mmMMEA5_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2920 #define mmMMEA5_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2921 #define mmMMEA5_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2922 #define mmMMEA5_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2923 #define mmMMEA5_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2924 #define mmMMEA5_SDP_ARB_DRAM_DEFAULT 0x00101e40 2925 #define mmMMEA5_SDP_ARB_GMI_DEFAULT 0x00101e40 2926 #define mmMMEA5_SDP_ARB_FINAL_DEFAULT 0x00007fff 2927 #define mmMMEA5_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 2928 #define mmMMEA5_SDP_GMI_PRIORITY_DEFAULT 0x00000000 2929 #define mmMMEA5_SDP_IO_PRIORITY_DEFAULT 0x00000000 2930 #define mmMMEA5_SDP_CREDITS_DEFAULT 0x000101bf 2931 #define mmMMEA5_SDP_TAG_RESERVE0_DEFAULT 0x00000000 2932 #define mmMMEA5_SDP_TAG_RESERVE1_DEFAULT 0x00000000 2933 #define mmMMEA5_SDP_VCC_RESERVE0_DEFAULT 0x00000000 2934 #define mmMMEA5_SDP_VCC_RESERVE1_DEFAULT 0x00000000 2935 #define mmMMEA5_SDP_VCD_RESERVE0_DEFAULT 0x00000000 2936 #define mmMMEA5_SDP_VCD_RESERVE1_DEFAULT 0x00000000 2937 #define mmMMEA5_SDP_REQ_CNTL_DEFAULT 0x0000001f 2938 #define mmMMEA5_MISC_DEFAULT 0x0c00a070 2939 #define mmMMEA5_LATENCY_SAMPLING_DEFAULT 0x00000000 2940 #define mmMMEA5_PERFCOUNTER_LO_DEFAULT 0x00000000 2941 #define mmMMEA5_PERFCOUNTER_HI_DEFAULT 0x00000000 2942 #define mmMMEA5_PERFCOUNTER0_CFG_DEFAULT 0x00000000 2943 #define mmMMEA5_PERFCOUNTER1_CFG_DEFAULT 0x00000000 2944 #define mmMMEA5_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 2945 #define mmMMEA5_EDC_CNT_DEFAULT 0x00000000 2946 #define mmMMEA5_EDC_CNT2_DEFAULT 0x00000000 2947 #define mmMMEA5_DSM_CNTL_DEFAULT 0x00000000 2948 #define mmMMEA5_DSM_CNTLA_DEFAULT 0x00000000 2949 #define mmMMEA5_DSM_CNTLB_DEFAULT 0x00000000 2950 #define mmMMEA5_DSM_CNTL2_DEFAULT 0x00000000 2951 #define mmMMEA5_DSM_CNTL2A_DEFAULT 0x00000000 2952 #define mmMMEA5_DSM_CNTL2B_DEFAULT 0x00000000 2953 #define mmMMEA5_CGTT_CLK_CTRL_DEFAULT 0x00000100 2954 #define mmMMEA5_EDC_MODE_DEFAULT 0x00000000 2955 #define mmMMEA5_ERR_STATUS_DEFAULT 0x00000300 2956 #define mmMMEA5_MISC2_DEFAULT 0x00000000 2957 #define mmMMEA5_ADDRDEC_SELECT_DEFAULT 0x00000000 2958 #define mmMMEA5_EDC_CNT3_DEFAULT 0x00000000 2959 2960 2961 // addressBlock: mmhub_ea_mmeadec6 2962 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 2963 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 2964 #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 2965 #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 2966 #define mmMMEA6_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 2967 #define mmMMEA6_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 2968 #define mmMMEA6_DRAM_RD_LAZY_DEFAULT 0x78000924 2969 #define mmMMEA6_DRAM_WR_LAZY_DEFAULT 0x78000924 2970 #define mmMMEA6_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 2971 #define mmMMEA6_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 2972 #define mmMMEA6_DRAM_PAGE_BURST_DEFAULT 0x20002000 2973 #define mmMMEA6_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 2974 #define mmMMEA6_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 2975 #define mmMMEA6_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 2976 #define mmMMEA6_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 2977 #define mmMMEA6_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 2978 #define mmMMEA6_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 2979 #define mmMMEA6_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 2980 #define mmMMEA6_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 2981 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2982 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2983 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2984 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 2985 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 2986 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 2987 #define mmMMEA6_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 2988 #define mmMMEA6_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 2989 #define mmMMEA6_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 2990 #define mmMMEA6_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 2991 #define mmMMEA6_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 2992 #define mmMMEA6_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 2993 #define mmMMEA6_GMI_RD_LAZY_DEFAULT 0x78000924 2994 #define mmMMEA6_GMI_WR_LAZY_DEFAULT 0x78000924 2995 #define mmMMEA6_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 2996 #define mmMMEA6_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 2997 #define mmMMEA6_GMI_PAGE_BURST_DEFAULT 0x20002000 2998 #define mmMMEA6_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 2999 #define mmMMEA6_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 3000 #define mmMMEA6_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 3001 #define mmMMEA6_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 3002 #define mmMMEA6_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 3003 #define mmMMEA6_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 3004 #define mmMMEA6_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 3005 #define mmMMEA6_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 3006 #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3007 #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3008 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3009 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3010 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3011 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3012 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3013 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3014 #define mmMMEA6_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 3015 #define mmMMEA6_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 3016 #define mmMMEA6_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 3017 #define mmMMEA6_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 3018 #define mmMMEA6_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 3019 #define mmMMEA6_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 3020 #define mmMMEA6_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 3021 #define mmMMEA6_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 3022 #define mmMMEA6_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 3023 #define mmMMEA6_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 3024 #define mmMMEA6_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 3025 #define mmMMEA6_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 3026 #define mmMMEA6_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 3027 #define mmMMEA6_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 3028 #define mmMMEA6_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 3029 #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 3030 #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 3031 #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 3032 #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 3033 #define mmMMEA6_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 3034 #define mmMMEA6_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 3035 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 3036 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 3037 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 3038 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 3039 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 3040 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 3041 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 3042 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 3043 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 3044 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 3045 #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 3046 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 3047 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 3048 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 3049 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 3050 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 3051 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 3052 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 3053 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 3054 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 3055 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 3056 #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 3057 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 3058 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 3059 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 3060 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 3061 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 3062 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 3063 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 3064 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 3065 #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 3066 #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 3067 #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 3068 #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 3069 #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 3070 #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 3071 #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 3072 #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 3073 #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 3074 #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 3075 #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 3076 #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 3077 #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 3078 #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 3079 #define mmMMEA6_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 3080 #define mmMMEA6_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 3081 #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 3082 #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 3083 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 3084 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 3085 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 3086 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 3087 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 3088 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 3089 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 3090 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 3091 #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 3092 #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 3093 #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 3094 #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 3095 #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 3096 #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 3097 #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 3098 #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 3099 #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 3100 #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 3101 #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 3102 #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 3103 #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 3104 #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 3105 #define mmMMEA6_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 3106 #define mmMMEA6_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 3107 #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 3108 #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 3109 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 3110 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 3111 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 3112 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 3113 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 3114 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 3115 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 3116 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 3117 #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 3118 #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 3119 #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 3120 #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 3121 #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 3122 #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 3123 #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 3124 #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 3125 #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 3126 #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 3127 #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 3128 #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 3129 #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 3130 #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 3131 #define mmMMEA6_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 3132 #define mmMMEA6_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 3133 #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 3134 #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 3135 #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 3136 #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 3137 #define mmMMEA6_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 3138 #define mmMMEA6_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 3139 #define mmMMEA6_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 3140 #define mmMMEA6_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 3141 #define mmMMEA6_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 3142 #define mmMMEA6_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 3143 #define mmMMEA6_IO_GROUP_BURST_DEFAULT 0x1f031f03 3144 #define mmMMEA6_IO_RD_PRI_AGE_DEFAULT 0x00db6249 3145 #define mmMMEA6_IO_WR_PRI_AGE_DEFAULT 0x00db6249 3146 #define mmMMEA6_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 3147 #define mmMMEA6_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 3148 #define mmMMEA6_IO_RD_PRI_FIXED_DEFAULT 0x00000924 3149 #define mmMMEA6_IO_WR_PRI_FIXED_DEFAULT 0x00000924 3150 #define mmMMEA6_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 3151 #define mmMMEA6_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 3152 #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3153 #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3154 #define mmMMEA6_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3155 #define mmMMEA6_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3156 #define mmMMEA6_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3157 #define mmMMEA6_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3158 #define mmMMEA6_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3159 #define mmMMEA6_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3160 #define mmMMEA6_SDP_ARB_DRAM_DEFAULT 0x00101e40 3161 #define mmMMEA6_SDP_ARB_GMI_DEFAULT 0x00101e40 3162 #define mmMMEA6_SDP_ARB_FINAL_DEFAULT 0x00007fff 3163 #define mmMMEA6_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 3164 #define mmMMEA6_SDP_GMI_PRIORITY_DEFAULT 0x00000000 3165 #define mmMMEA6_SDP_IO_PRIORITY_DEFAULT 0x00000000 3166 #define mmMMEA6_SDP_CREDITS_DEFAULT 0x000101bf 3167 #define mmMMEA6_SDP_TAG_RESERVE0_DEFAULT 0x00000000 3168 #define mmMMEA6_SDP_TAG_RESERVE1_DEFAULT 0x00000000 3169 #define mmMMEA6_SDP_VCC_RESERVE0_DEFAULT 0x00000000 3170 #define mmMMEA6_SDP_VCC_RESERVE1_DEFAULT 0x00000000 3171 #define mmMMEA6_SDP_VCD_RESERVE0_DEFAULT 0x00000000 3172 #define mmMMEA6_SDP_VCD_RESERVE1_DEFAULT 0x00000000 3173 #define mmMMEA6_SDP_REQ_CNTL_DEFAULT 0x0000001f 3174 #define mmMMEA6_MISC_DEFAULT 0x0c00a070 3175 #define mmMMEA6_LATENCY_SAMPLING_DEFAULT 0x00000000 3176 #define mmMMEA6_PERFCOUNTER_LO_DEFAULT 0x00000000 3177 #define mmMMEA6_PERFCOUNTER_HI_DEFAULT 0x00000000 3178 #define mmMMEA6_PERFCOUNTER0_CFG_DEFAULT 0x00000000 3179 #define mmMMEA6_PERFCOUNTER1_CFG_DEFAULT 0x00000000 3180 #define mmMMEA6_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 3181 #define mmMMEA6_EDC_CNT_DEFAULT 0x00000000 3182 #define mmMMEA6_EDC_CNT2_DEFAULT 0x00000000 3183 #define mmMMEA6_DSM_CNTL_DEFAULT 0x00000000 3184 #define mmMMEA6_DSM_CNTLA_DEFAULT 0x00000000 3185 #define mmMMEA6_DSM_CNTLB_DEFAULT 0x00000000 3186 #define mmMMEA6_DSM_CNTL2_DEFAULT 0x00000000 3187 #define mmMMEA6_DSM_CNTL2A_DEFAULT 0x00000000 3188 #define mmMMEA6_DSM_CNTL2B_DEFAULT 0x00000000 3189 #define mmMMEA6_CGTT_CLK_CTRL_DEFAULT 0x00000100 3190 #define mmMMEA6_EDC_MODE_DEFAULT 0x00000000 3191 #define mmMMEA6_ERR_STATUS_DEFAULT 0x00000300 3192 #define mmMMEA6_MISC2_DEFAULT 0x00000000 3193 #define mmMMEA6_ADDRDEC_SELECT_DEFAULT 0x00000000 3194 #define mmMMEA6_EDC_CNT3_DEFAULT 0x00000000 3195 3196 3197 // addressBlock: mmhub_ea_mmeadec7 3198 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 3199 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 3200 #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 3201 #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 3202 #define mmMMEA7_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 3203 #define mmMMEA7_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 3204 #define mmMMEA7_DRAM_RD_LAZY_DEFAULT 0x78000924 3205 #define mmMMEA7_DRAM_WR_LAZY_DEFAULT 0x78000924 3206 #define mmMMEA7_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 3207 #define mmMMEA7_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 3208 #define mmMMEA7_DRAM_PAGE_BURST_DEFAULT 0x20002000 3209 #define mmMMEA7_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 3210 #define mmMMEA7_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 3211 #define mmMMEA7_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 3212 #define mmMMEA7_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 3213 #define mmMMEA7_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 3214 #define mmMMEA7_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 3215 #define mmMMEA7_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 3216 #define mmMMEA7_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 3217 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3218 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3219 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3220 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3221 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3222 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3223 #define mmMMEA7_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 3224 #define mmMMEA7_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 3225 #define mmMMEA7_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 3226 #define mmMMEA7_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 3227 #define mmMMEA7_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff 3228 #define mmMMEA7_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff 3229 #define mmMMEA7_GMI_RD_LAZY_DEFAULT 0x78000924 3230 #define mmMMEA7_GMI_WR_LAZY_DEFAULT 0x78000924 3231 #define mmMMEA7_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 3232 #define mmMMEA7_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 3233 #define mmMMEA7_GMI_PAGE_BURST_DEFAULT 0x20002000 3234 #define mmMMEA7_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 3235 #define mmMMEA7_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 3236 #define mmMMEA7_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 3237 #define mmMMEA7_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 3238 #define mmMMEA7_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 3239 #define mmMMEA7_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 3240 #define mmMMEA7_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 3241 #define mmMMEA7_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 3242 #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3243 #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3244 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3245 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3246 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3247 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3248 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3249 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3250 #define mmMMEA7_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 3251 #define mmMMEA7_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 3252 #define mmMMEA7_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 3253 #define mmMMEA7_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 3254 #define mmMMEA7_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 3255 #define mmMMEA7_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 3256 #define mmMMEA7_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 3257 #define mmMMEA7_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 3258 #define mmMMEA7_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 3259 #define mmMMEA7_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 3260 #define mmMMEA7_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 3261 #define mmMMEA7_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 3262 #define mmMMEA7_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 3263 #define mmMMEA7_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 3264 #define mmMMEA7_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 3265 #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 3266 #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 3267 #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 3268 #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 3269 #define mmMMEA7_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf 3270 #define mmMMEA7_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 3271 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 3272 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 3273 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 3274 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 3275 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 3276 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 3277 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 3278 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 3279 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 3280 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 3281 #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 3282 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 3283 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 3284 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 3285 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 3286 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 3287 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 3288 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 3289 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 3290 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 3291 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 3292 #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 3293 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 3294 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 3295 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 3296 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 3297 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 3298 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 3299 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 3300 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 3301 #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 3302 #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 3303 #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 3304 #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 3305 #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 3306 #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 3307 #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 3308 #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 3309 #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 3310 #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 3311 #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 3312 #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 3313 #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 3314 #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 3315 #define mmMMEA7_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 3316 #define mmMMEA7_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 3317 #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 3318 #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 3319 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 3320 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 3321 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 3322 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 3323 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 3324 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 3325 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 3326 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 3327 #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 3328 #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 3329 #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 3330 #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 3331 #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 3332 #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 3333 #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 3334 #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 3335 #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 3336 #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 3337 #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 3338 #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 3339 #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 3340 #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 3341 #define mmMMEA7_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 3342 #define mmMMEA7_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 3343 #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 3344 #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 3345 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 3346 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 3347 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 3348 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 3349 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 3350 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 3351 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 3352 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 3353 #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe 3354 #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe 3355 #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 3356 #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 3357 #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 3358 #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 3359 #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 3360 #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 3361 #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 3362 #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 3363 #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 3364 #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 3365 #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 3366 #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 3367 #define mmMMEA7_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 3368 #define mmMMEA7_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 3369 #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 3370 #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 3371 #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 3372 #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 3373 #define mmMMEA7_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 3374 #define mmMMEA7_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 3375 #define mmMMEA7_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 3376 #define mmMMEA7_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 3377 #define mmMMEA7_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 3378 #define mmMMEA7_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 3379 #define mmMMEA7_IO_GROUP_BURST_DEFAULT 0x1f031f03 3380 #define mmMMEA7_IO_RD_PRI_AGE_DEFAULT 0x00db6249 3381 #define mmMMEA7_IO_WR_PRI_AGE_DEFAULT 0x00db6249 3382 #define mmMMEA7_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 3383 #define mmMMEA7_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 3384 #define mmMMEA7_IO_RD_PRI_FIXED_DEFAULT 0x00000924 3385 #define mmMMEA7_IO_WR_PRI_FIXED_DEFAULT 0x00000924 3386 #define mmMMEA7_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 3387 #define mmMMEA7_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 3388 #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3389 #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 3390 #define mmMMEA7_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3391 #define mmMMEA7_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3392 #define mmMMEA7_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3393 #define mmMMEA7_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 3394 #define mmMMEA7_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 3395 #define mmMMEA7_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 3396 #define mmMMEA7_SDP_ARB_DRAM_DEFAULT 0x00101e40 3397 #define mmMMEA7_SDP_ARB_GMI_DEFAULT 0x00101e40 3398 #define mmMMEA7_SDP_ARB_FINAL_DEFAULT 0x00007fff 3399 #define mmMMEA7_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 3400 #define mmMMEA7_SDP_GMI_PRIORITY_DEFAULT 0x00000000 3401 #define mmMMEA7_SDP_IO_PRIORITY_DEFAULT 0x00000000 3402 #define mmMMEA7_SDP_CREDITS_DEFAULT 0x000101bf 3403 #define mmMMEA7_SDP_TAG_RESERVE0_DEFAULT 0x00000000 3404 #define mmMMEA7_SDP_TAG_RESERVE1_DEFAULT 0x00000000 3405 #define mmMMEA7_SDP_VCC_RESERVE0_DEFAULT 0x00000000 3406 #define mmMMEA7_SDP_VCC_RESERVE1_DEFAULT 0x00000000 3407 #define mmMMEA7_SDP_VCD_RESERVE0_DEFAULT 0x00000000 3408 #define mmMMEA7_SDP_VCD_RESERVE1_DEFAULT 0x00000000 3409 #define mmMMEA7_SDP_REQ_CNTL_DEFAULT 0x0000001f 3410 #define mmMMEA7_MISC_DEFAULT 0x0c00a070 3411 #define mmMMEA7_LATENCY_SAMPLING_DEFAULT 0x00000000 3412 #define mmMMEA7_PERFCOUNTER_LO_DEFAULT 0x00000000 3413 #define mmMMEA7_PERFCOUNTER_HI_DEFAULT 0x00000000 3414 #define mmMMEA7_PERFCOUNTER0_CFG_DEFAULT 0x00000000 3415 #define mmMMEA7_PERFCOUNTER1_CFG_DEFAULT 0x00000000 3416 #define mmMMEA7_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 3417 #define mmMMEA7_EDC_CNT_DEFAULT 0x00000000 3418 #define mmMMEA7_EDC_CNT2_DEFAULT 0x00000000 3419 #define mmMMEA7_DSM_CNTL_DEFAULT 0x00000000 3420 #define mmMMEA7_DSM_CNTLA_DEFAULT 0x00000000 3421 #define mmMMEA7_DSM_CNTLB_DEFAULT 0x00000000 3422 #define mmMMEA7_DSM_CNTL2_DEFAULT 0x00000000 3423 #define mmMMEA7_DSM_CNTL2A_DEFAULT 0x00000000 3424 #define mmMMEA7_DSM_CNTL2B_DEFAULT 0x00000000 3425 #define mmMMEA7_CGTT_CLK_CTRL_DEFAULT 0x00000100 3426 #define mmMMEA7_EDC_MODE_DEFAULT 0x00000000 3427 #define mmMMEA7_ERR_STATUS_DEFAULT 0x00000300 3428 #define mmMMEA7_MISC2_DEFAULT 0x00000000 3429 #define mmMMEA7_ADDRDEC_SELECT_DEFAULT 0x00000000 3430 #define mmMMEA7_EDC_CNT3_DEFAULT 0x00000000 3431 3432 3433 // addressBlock: mmhub_pctldec1 3434 #define mmPCTL1_CTRL_DEFAULT 0x00011040 3435 #define mmPCTL1_MMHUB_DEEPSLEEP_IB_DEFAULT 0x00000000 3436 #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 3437 #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT 0x00000000 3438 #define mmPCTL1_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 3439 #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_DEFAULT 0x00000000 3440 #define mmPCTL1_SLICE0_CFG_DAGB_BUSY_DEFAULT 0x00000000 3441 #define mmPCTL1_SLICE0_CFG_DS_ALLOW_DEFAULT 0x00000000 3442 #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 3443 #define mmPCTL1_SLICE1_CFG_DAGB_BUSY_DEFAULT 0x00000000 3444 #define mmPCTL1_SLICE1_CFG_DS_ALLOW_DEFAULT 0x00000000 3445 #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 3446 #define mmPCTL1_SLICE2_CFG_DAGB_BUSY_DEFAULT 0x00000000 3447 #define mmPCTL1_SLICE2_CFG_DS_ALLOW_DEFAULT 0x00000000 3448 #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 3449 #define mmPCTL1_SLICE3_CFG_DAGB_BUSY_DEFAULT 0x00000000 3450 #define mmPCTL1_SLICE3_CFG_DS_ALLOW_DEFAULT 0x00000000 3451 #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 3452 #define mmPCTL1_SLICE4_CFG_DAGB_BUSY_DEFAULT 0x00000000 3453 #define mmPCTL1_SLICE4_CFG_DS_ALLOW_DEFAULT 0x00000000 3454 #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 3455 #define mmPCTL1_UTCL2_MISC_DEFAULT 0x00011000 3456 #define mmPCTL1_SLICE0_MISC_DEFAULT 0x00000800 3457 #define mmPCTL1_SLICE1_MISC_DEFAULT 0x00000800 3458 #define mmPCTL1_SLICE2_MISC_DEFAULT 0x00000800 3459 #define mmPCTL1_SLICE3_MISC_DEFAULT 0x00000800 3460 #define mmPCTL1_SLICE4_MISC_DEFAULT 0x00000800 3461 #define mmPCTL1_UTCL2_RENG_EXECUTE_DEFAULT 0x00000000 3462 #define mmPCTL1_SLICE0_RENG_EXECUTE_DEFAULT 0x00000000 3463 #define mmPCTL1_SLICE1_RENG_EXECUTE_DEFAULT 0x00000000 3464 #define mmPCTL1_SLICE2_RENG_EXECUTE_DEFAULT 0x00000000 3465 #define mmPCTL1_SLICE3_RENG_EXECUTE_DEFAULT 0x00000000 3466 #define mmPCTL1_SLICE4_RENG_EXECUTE_DEFAULT 0x00000000 3467 #define mmPCTL1_UTCL2_RENG_RAM_INDEX_DEFAULT 0x00000000 3468 #define mmPCTL1_UTCL2_RENG_RAM_DATA_DEFAULT 0x00000000 3469 #define mmPCTL1_SLICE0_RENG_RAM_INDEX_DEFAULT 0x00000000 3470 #define mmPCTL1_SLICE0_RENG_RAM_DATA_DEFAULT 0x00000000 3471 #define mmPCTL1_SLICE1_RENG_RAM_INDEX_DEFAULT 0x00000000 3472 #define mmPCTL1_SLICE1_RENG_RAM_DATA_DEFAULT 0x00000000 3473 #define mmPCTL1_SLICE2_RENG_RAM_INDEX_DEFAULT 0x00000000 3474 #define mmPCTL1_SLICE2_RENG_RAM_DATA_DEFAULT 0x00000000 3475 #define mmPCTL1_SLICE3_RENG_RAM_INDEX_DEFAULT 0x00000000 3476 #define mmPCTL1_SLICE3_RENG_RAM_DATA_DEFAULT 0x00000000 3477 #define mmPCTL1_SLICE4_RENG_RAM_INDEX_DEFAULT 0x00000000 3478 #define mmPCTL1_SLICE4_RENG_RAM_DATA_DEFAULT 0x00000000 3479 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 3480 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 3481 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 3482 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 3483 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 3484 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 3485 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 3486 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 3487 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 3488 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 3489 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 3490 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 3491 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 3492 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 3493 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 3494 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 3495 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 3496 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 3497 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 3498 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 3499 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 3500 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 3501 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 3502 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 3503 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 3504 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 3505 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 3506 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 3507 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 3508 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 3509 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 3510 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 3511 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 3512 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 3513 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 3514 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 3515 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 3516 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 3517 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 3518 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 3519 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff 3520 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 3521 3522 3523 // addressBlock: mmhub_l1tlb_vml1dec:1 3524 #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 3525 #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 3526 #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 3527 #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 3528 #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 3529 #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 3530 #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 3531 #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 3532 #define mmVML1_1_MC_VM_MX_L1_TMZ_CNTL_DEFAULT 0x00000000 3533 3534 3535 // addressBlock: mmhub_l1tlb_vml1pldec:1 3536 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 3537 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 3538 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 3539 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 3540 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 3541 3542 3543 // addressBlock: mmhub_l1tlb_vml1prdec:1 3544 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 3545 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 3546 3547 3548 // addressBlock: mmhub_utcl2_atcl2dec:1 3549 #define mmATCL2_1_ATC_L2_CNTL_DEFAULT 0x0001c0c9 3550 #define mmATCL2_1_ATC_L2_CNTL2_DEFAULT 0x00600100 3551 #define mmATCL2_1_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 3552 #define mmATCL2_1_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 3553 #define mmATCL2_1_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 3554 #define mmATCL2_1_ATC_L2_CNTL3_DEFAULT 0x000001f8 3555 #define mmATCL2_1_ATC_L2_STATUS_DEFAULT 0x00000000 3556 #define mmATCL2_1_ATC_L2_STATUS2_DEFAULT 0x00000000 3557 #define mmATCL2_1_ATC_L2_STATUS3_DEFAULT 0x00000000 3558 #define mmATCL2_1_ATC_L2_MISC_CG_DEFAULT 0x00000200 3559 #define mmATCL2_1_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 3560 #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 3561 #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT 0x00000000 3562 #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT 0x00000000 3563 #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT 0x00000000 3564 #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT 0x00000000 3565 #define mmATCL2_1_ATC_L2_CNTL4_DEFAULT 0x00000000 3566 #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000005 3567 3568 3569 // addressBlock: mmhub_utcl2_vml2pfdec:1 3570 #define mmVML2PF1_VM_L2_CNTL_DEFAULT 0x00080602 3571 #define mmVML2PF1_VM_L2_CNTL2_DEFAULT 0x00000000 3572 #define mmVML2PF1_VM_L2_CNTL3_DEFAULT 0x80100007 3573 #define mmVML2PF1_VM_L2_STATUS_DEFAULT 0x00000000 3574 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 3575 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 3576 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 3577 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc 3578 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 3579 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff 3580 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff 3581 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 3582 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 3583 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 3584 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 3585 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 3586 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 3587 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 3588 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 3589 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 3590 #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 3591 #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 3592 #define mmVML2PF1_VM_L2_CNTL4_DEFAULT 0x000000c1 3593 #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 3594 #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 3595 #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 3596 #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 3597 #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 3598 3599 3600 // addressBlock: mmhub_utcl2_vml2vcdec:1 3601 #define mmVML2VC1_VM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 3602 #define mmVML2VC1_VM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 3603 #define mmVML2VC1_VM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 3604 #define mmVML2VC1_VM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 3605 #define mmVML2VC1_VM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 3606 #define mmVML2VC1_VM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 3607 #define mmVML2VC1_VM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 3608 #define mmVML2VC1_VM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 3609 #define mmVML2VC1_VM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 3610 #define mmVML2VC1_VM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 3611 #define mmVML2VC1_VM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 3612 #define mmVML2VC1_VM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 3613 #define mmVML2VC1_VM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 3614 #define mmVML2VC1_VM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 3615 #define mmVML2VC1_VM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 3616 #define mmVML2VC1_VM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 3617 #define mmVML2VC1_VM_CONTEXTS_DISABLE_DEFAULT 0x00000000 3618 #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 3619 #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 3620 #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 3621 #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 3622 #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 3623 #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 3624 #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 3625 #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 3626 #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 3627 #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 3628 #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 3629 #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 3630 #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 3631 #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 3632 #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 3633 #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 3634 #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 3635 #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 3636 #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 3637 #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 3638 #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 3639 #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 3640 #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 3641 #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 3642 #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 3643 #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 3644 #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 3645 #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 3646 #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 3647 #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 3648 #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 3649 #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 3650 #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 3651 #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 3652 #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 3653 #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 3654 #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 3655 #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 3656 #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 3657 #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 3658 #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 3659 #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 3660 #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 3661 #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 3662 #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 3663 #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 3664 #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 3665 #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 3666 #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 3667 #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 3668 #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 3669 #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 3670 #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 3671 #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 3672 #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 3673 #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 3674 #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 3675 #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 3676 #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 3677 #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 3678 #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 3679 #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 3680 #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 3681 #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 3682 #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 3683 #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 3684 #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 3685 #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 3686 #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 3687 #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 3688 #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 3689 #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 3690 #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 3691 #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 3692 #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 3693 #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 3694 #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 3695 #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 3696 #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 3697 #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 3698 #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 3699 #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 3700 #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 3701 #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 3702 #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 3703 #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 3704 #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 3705 #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 3706 #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 3707 #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 3708 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3709 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3710 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3711 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3712 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3713 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3714 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3715 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3716 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3717 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3718 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3719 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3720 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3721 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3722 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3723 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3724 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3725 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3726 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3727 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3728 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3729 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3730 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3731 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3732 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3733 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3734 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3735 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3736 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3737 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3738 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 3739 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 3740 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3741 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3742 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3743 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3744 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3745 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3746 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3747 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3748 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3749 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3750 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3751 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3752 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3753 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3754 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3755 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3756 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3757 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3758 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3759 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3760 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3761 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3762 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3763 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3764 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3765 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3766 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3767 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3768 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3769 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3770 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 3771 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 3772 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3773 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3774 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3775 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3776 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3777 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3778 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3779 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3780 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3781 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3782 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3783 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3784 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3785 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3786 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3787 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3788 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3789 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3790 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3791 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3792 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3793 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3794 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3795 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3796 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3797 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3798 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3799 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3800 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3801 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3802 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 3803 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 3804 3805 3806 // addressBlock: mmhub_utcl2_vmsharedpfdec:1 3807 #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_DEFAULT 0x00000000 3808 #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 3809 #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 3810 #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_DEFAULT 0x00000008 3811 #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 3812 #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 3813 #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 3814 #define mmVMSHAREDPF1_MC_VM_FB_OFFSET_DEFAULT 0x00000000 3815 #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 3816 #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 3817 #define mmVMSHAREDPF1_MC_VM_STEERING_DEFAULT 0x00000001 3818 #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 3819 #define mmVMSHAREDPF1_MC_MEM_POWER_LS_DEFAULT 0x00000208 3820 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 3821 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 3822 #define mmVMSHAREDPF1_MC_VM_APT_CNTL_DEFAULT 0x00000000 3823 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 3824 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff 3825 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 3826 #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_DEFAULT 0x00000000 3827 #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_DEFAULT 0x00000000 3828 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT 0x00000000 3829 3830 3831 // addressBlock: mmhub_utcl2_vmsharedvcdec:1 3832 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 3833 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 3834 #define mmVMSHAREDVC1_MC_VM_AGP_TOP_DEFAULT 0x00000000 3835 #define mmVMSHAREDVC1_MC_VM_AGP_BOT_DEFAULT 0x00000000 3836 #define mmVMSHAREDVC1_MC_VM_AGP_BASE_DEFAULT 0x00000000 3837 #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 3838 #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 3839 #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 3840 3841 3842 // addressBlock: mmhub_utcl2_vmsharedhvdec:1 3843 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 3844 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 3845 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 3846 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 3847 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 3848 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 3849 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 3850 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 3851 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 3852 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 3853 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 3854 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 3855 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 3856 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 3857 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 3858 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 3859 #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 3860 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 3861 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 3862 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 3863 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 3864 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 3865 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 3866 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 3867 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 3868 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 3869 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 3870 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 3871 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 3872 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 3873 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 3874 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 3875 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 3876 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 3877 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 3878 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 3879 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 3880 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 3881 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 3882 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 3883 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 3884 #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 3885 #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 3886 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_DEFAULT 0x00000000 3887 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 3888 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 3889 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 3890 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 3891 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 3892 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 3893 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 3894 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 3895 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 3896 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 3897 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 3898 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 3899 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 3900 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 3901 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 3902 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 3903 #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 3904 #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 3905 #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT 0x00000000 3906 3907 3908 // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 3909 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 3910 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 3911 3912 3913 // addressBlock: mmhub_utcl2_atcl2pfcntldec:1 3914 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 3915 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 3916 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 3917 3918 3919 // addressBlock: mmhub_utcl2_vml2pldec:1 3920 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 3921 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 3922 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 3923 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 3924 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 3925 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 3926 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 3927 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 3928 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 3929 3930 3931 // addressBlock: mmhub_utcl2_vml2prdec:1 3932 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 3933 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 3934 3935 #endif 3936
Indexes created Sat Sep 20 22:09:52 GMT 2025