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    Searched refs:mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_ai.c 149 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
nbio_6_1_offset.h 2606 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137

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