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Searched refs:mmBIF_BX_PF_MAILBOX_CONTROL (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
mxgpu_nv.h	`40 #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4) 41 #define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4 + 1)`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
nbio_2_3_offset.h	`606 #define mmBIF_BX_PF_MAILBOX_CONTROL 0x013e [all...]`

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