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    Searched refs:mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_nv.c 155 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3),
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
nbio_2_3_offset.h 596 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x0139
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