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Searched refs:mmBPHYC_PLL0_VGA25_PPLL_POST_DIV (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_10_0_d.h	`6140 #define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718`
dce_11_0_d.h	`6217 #define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718`

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