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    Searched refs:mmCB_HW_CONTROL_2 (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
amdgpu_gfx_v8_0.c 318 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
349 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
381 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 281 #define mmCB_HW_CONTROL_2 0x2686
gfx_7_0_d.h 142 #define mmCB_HW_CONTROL_2 0x2686
gfx_7_2_d.h 142 #define mmCB_HW_CONTROL_2 0x2686
gfx_8_0_d.h 159 #define mmCB_HW_CONTROL_2 0x2686
gfx_8_1_d.h 159 #define mmCB_HW_CONTROL_2 0x2686
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 1044 #define mmCB_HW_CONTROL_2 0x0682
gc_9_1_offset.h 1014 #define mmCB_HW_CONTROL_2 0x0682
gc_9_2_1_offset.h 980 #define mmCB_HW_CONTROL_2 0x0682
gc_10_1_0_offset.h 2962 #define mmCB_HW_CONTROL_2 0x1426
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