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Searched refs:mmCGTS_CU0_TA_SQC_CTRL_REG (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_vi.c	`177 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,`
amdgpu_gfx_v8_0.c	`271 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 545 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 641 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`1489 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a`
gfx_7_2_d.h	`1510 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a`
gfx_8_0_d.h	`1703 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a`
gfx_8_1_d.h	`1671 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`6314 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a`
gc_9_1_offset.h	`6536 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a`
gc_9_2_1_offset.h	`6548 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a`

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