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Searched refs:mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`6367 #define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1`
gc_9_1_offset.h	`6589 #define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1`
gc_9_2_1_offset.h	`6601 #define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1`

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