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    Searched refs:mmCGTS_CU9_SP1_CTRL_REG (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 1535 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038
gfx_7_2_d.h 1556 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038
gfx_8_0_d.h 1749 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038
gfx_8_1_d.h 1717 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6406 #define mmCGTS_CU9_SP1_CTRL_REG 0x5038
gc_9_1_offset.h 6628 #define mmCGTS_CU9_SP1_CTRL_REG 0x5038
gc_9_2_1_offset.h 6640 #define mmCGTS_CU9_SP1_CTRL_REG 0x5038

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