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    Searched refs:mmCGTS_USER_TCC_DISABLE (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 302 #define mmCGTS_USER_TCC_DISABLE 0x2453
gfx_7_0_d.h 1486 #define mmCGTS_USER_TCC_DISABLE 0xf004
gfx_7_2_d.h 1507 #define mmCGTS_USER_TCC_DISABLE 0xf004
gfx_8_0_d.h 1700 #define mmCGTS_USER_TCC_DISABLE 0xf004
gfx_8_1_d.h 1668 #define mmCGTS_USER_TCC_DISABLE 0xf004
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 1725 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6308 #define mmCGTS_USER_TCC_DISABLE 0x5004
gc_9_1_offset.h 6530 #define mmCGTS_USER_TCC_DISABLE 0x5004
gc_9_2_1_offset.h 6542 #define mmCGTS_USER_TCC_DISABLE 0x5004
gc_10_1_0_offset.h 9898 #define mmCGTS_USER_TCC_DISABLE 0x500b
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