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    Searched refs:mmCG_FDO_CTRL0 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/thm/
thm_11_0_2_offset.h 31 #define mmCG_FDO_CTRL0 0x0067
thm_9_0_offset.h 204 #define mmCG_FDO_CTRL0 0x0062
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega20_thermal.c 165 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
amdgpu_vega10_thermal.c 283 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
284 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v11_0.c 1454 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1455 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

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