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Searched refs:mmCPC_INT_CNTL (Results 1 - 13 of 13) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c	`204 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),`
amdgpu_amdkfd_gfx_v7.c	`211 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK \|`
amdgpu_amdkfd_gfx_v8.c	`169 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK \|`
amdgpu_amdkfd_gfx_v9.c	`214 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),`
amdgpu_gfx_v10_0.c	`5088 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5091 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5098 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5101 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`266 #define mmCPC_INT_CNTL 0x30b4`
gfx_7_2_d.h	`268 #define mmCPC_INT_CNTL 0x30b4`
gfx_8_0_d.h	`299 #define mmCPC_INT_CNTL 0x30b4`
gfx_8_1_d.h	`299 #define mmCPC_INT_CNTL 0x30b4`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2590 #define mmCPC_INT_CNTL 0x10b4`
gc_9_1_offset.h	`2860 #define mmCPC_INT_CNTL 0x10b4`
gc_9_2_1_offset.h	`2794 #define mmCPC_INT_CNTL 0x10b4`
gc_10_1_0_offset.h	`4928 #define mmCPC_INT_CNTL 0x1e54 [all...]`

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