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Searched refs:mmCPC_INT_STATUS (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`275 #define mmCPC_INT_STATUS 0x30b5`
gfx_7_2_d.h	`277 #define mmCPC_INT_STATUS 0x30b5`
gfx_8_0_d.h	`308 #define mmCPC_INT_STATUS 0x30b5`
gfx_8_1_d.h	`308 #define mmCPC_INT_STATUS 0x30b5`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`4562 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));`
amdgpu_gfx_v8_0.c	`6385 amdgpu_ring_write(ring, mmCPC_INT_STATUS);`
amdgpu_gfx_v9_0.c	`5186 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2592 #define mmCPC_INT_STATUS 0x10b5`
gc_9_1_offset.h	`2862 #define mmCPC_INT_STATUS 0x10b5`
gc_9_2_1_offset.h	`2796 #define mmCPC_INT_STATUS 0x10b5`
gc_10_1_0_offset.h	`4930 #define mmCPC_INT_STATUS 0x1e55 [all...]`

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