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    Searched refs:mmCPF_EDC_ROQ_CNT (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 119 #define mmCPF_EDC_ROQ_CNT 0x118a
gc_9_0_offset.h 2638 #define mmCPF_EDC_ROQ_CNT 0x118a
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_4.c 54 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
154 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
157 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
amdgpu_gfx_v9_0.c 4119 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1},
5649 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5653 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
amdgpu_gfx_v8_0.c 1499 mmCPF_EDC_ROQ_CNT,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h 2816 #define mmCPF_EDC_ROQ_CNT 0x3189

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