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Searched refs:mmCP_CPC_IC_BASE_HI (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c	`219 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`2344 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2944 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,`
amdgpu_gfx_v9_0.c	`3287 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h	`349 #define mmCP_CPC_IC_BASE_HI 0x30ba`
gfx_8_1_d.h	`349 #define mmCP_CPC_IC_BASE_HI 0x30ba`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h	`61 { 0x000000b4, mmCP_CPC_IC_BASE_HI },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2602 #define mmCP_CPC_IC_BASE_HI 0x10ba`
gc_9_1_offset.h	`2872 #define mmCP_CPC_IC_BASE_HI 0x10ba`
gc_9_2_1_offset.h	`2806 #define mmCP_CPC_IC_BASE_HI 0x10ba`
gc_10_1_0_offset.h	`[all...]`

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