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Searched refs:mmCP_DFY_CNTL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu7_smumgr.c	`527 cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`177 #define mmCP_DFY_CNTL 0x3020`
gfx_7_2_d.h	`177 #define mmCP_DFY_CNTL 0x3020`
gfx_8_0_d.h	`199 #define mmCP_DFY_CNTL 0x3020`
gfx_8_1_d.h	`199 #define mmCP_DFY_CNTL 0x3020`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h	`55 { 0x80000004, mmCP_DFY_CNTL },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2295 #define mmCP_DFY_CNTL 0x1020`
gc_9_1_offset.h	`2572 #define mmCP_DFY_CNTL 0x1020`
gc_9_2_1_offset.h	`2510 #define mmCP_DFY_CNTL 0x1020`

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