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    Searched refs:mmCP_DFY_DATA_0 (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu7_smumgr.c 531 cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 181 #define mmCP_DFY_DATA_0 0x3024
gfx_7_2_d.h 181 #define mmCP_DFY_DATA_0 0x3024
gfx_8_0_d.h 203 #define mmCP_DFY_DATA_0 0x3024
gfx_8_1_d.h 203 #define mmCP_DFY_DATA_0 0x3024
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2303 #define mmCP_DFY_DATA_0 0x1024
gc_9_1_offset.h 2580 #define mmCP_DFY_DATA_0 0x1024
gc_9_2_1_offset.h 2518 #define mmCP_DFY_DATA_0 0x1024

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