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    Searched refs:mmCP_GFX_HQD_WPTR (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 3071 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3072 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_offset.h 5036 #define mmCP_GFX_HQD_WPTR 0x1e91
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