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    Searched refs:mmCP_GFX_MQD_CONTROL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 2995 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
3080 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2654 #define mmCP_GFX_MQD_CONTROL 0x11a0
gc_9_1_offset.h 2906 #define mmCP_GFX_MQD_CONTROL 0x11a0
gc_9_2_1_offset.h 2840 #define mmCP_GFX_MQD_CONTROL 0x11a0
gc_10_1_0_offset.h 5050 #define mmCP_GFX_MQD_CONTROL 0x1e9a
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