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    Searched refs:mmCP_HQD_ACTIVE (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1547 { 0x00000000, mmCP_HQD_ACTIVE },
1550 { 0x00000001, mmCP_HQD_ACTIVE },
1552 { 0x00000000, mmCP_HQD_ACTIVE },
1555 { 0x00000001, mmCP_HQD_ACTIVE },
1557 { 0x00000000, mmCP_HQD_ACTIVE },
1560 { 0x00000001, mmCP_HQD_ACTIVE },
1562 { 0x00000000, mmCP_HQD_ACTIVE },
1565 { 0x00000001, mmCP_HQD_ACTIVE },
1567 { 0x00000000, mmCP_HQD_ACTIVE },
1570 { 0x00000001, mmCP_HQD_ACTIVE },
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 337 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
540 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
665 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
amdgpu_amdkfd_gfx_v7.c 281 WREG32(mmCP_HQD_ACTIVE, data);
416 act = RREG32(mmCP_HQD_ACTIVE);
534 temp = RREG32(mmCP_HQD_ACTIVE);
amdgpu_amdkfd_gfx_v8.c 268 WREG32(mmCP_HQD_ACTIVE, data);
411 act = RREG32(mmCP_HQD_ACTIVE);
532 temp = RREG32(mmCP_HQD_ACTIVE);
amdgpu_amdkfd_gfx_v9.c 325 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
528 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
595 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
amdgpu_gfx_v9_0.c 3487 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3490 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3560 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,
3575 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3580 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3589 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
amdgpu_gfx_v10_0.c 3380 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3383 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3453 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
amdgpu_gfx_v7_0.c 2917 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2920 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3075 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
amdgpu_gfx_v8_0.c 4415 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4418 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4609 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 571 #define mmCP_HQD_ACTIVE 0x3247
gfx_7_2_d.h 584 #define mmCP_HQD_ACTIVE 0x3247
gfx_8_0_d.h 634 #define mmCP_HQD_ACTIVE 0x3247
gfx_8_1_d.h 634 #define mmCP_HQD_ACTIVE 0x3247
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2820 #define mmCP_HQD_ACTIVE 0x1247
gc_9_1_offset.h 3048 #define mmCP_HQD_ACTIVE 0x1247
gc_9_2_1_offset.h 3004 #define mmCP_HQD_ACTIVE 0x1247
gc_10_1_0_offset.h 5286 #define mmCP_HQD_ACTIVE 0x1fab
    [all...]

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