HomeSort by: relevance | last modified time | path
    Searched refs:mmCP_HQD_EOP_CONTROL (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v8.c 233 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
amdgpu_gfx_v10_0.c 3242 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3372 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
amdgpu_gfx_v8_0.c 4455 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4591 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
amdgpu_gfx_v9_0.c 3350 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3479 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h 674 #define mmCP_HQD_EOP_CONTROL 0x326c
gfx_8_1_d.h 674 #define mmCP_HQD_EOP_CONTROL 0x326c
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2898 #define mmCP_HQD_EOP_CONTROL 0x126c
gc_9_1_offset.h 3126 #define mmCP_HQD_EOP_CONTROL 0x126c
gc_9_2_1_offset.h 3082 #define mmCP_HQD_EOP_CONTROL 0x126c
gc_10_1_0_offset.h 5364 #define mmCP_HQD_EOP_CONTROL 0x1fd0
    [all...]

Completed in 201 milliseconds